SDRAM (Synchronous Dynamic RAM) is a type of volatile DRAM that synchronizes its internal operations to an external clock signal, allowing the memory controller and the RAM to pipeline transfers and sustain higher bandwidth than asynchronous DRAM. Unlike SRAM, SDRAM stores each bit as a charge in a capacitor and requires periodic refresh cycles to retain data.
In practice
SDRAM appears in embedded designs that need megabytes to gigabytes of fast, dense, low-cost RAM -- far more than on-chip SRAM can typically provide. Common consumers include frame buffers for displays, audio/video codec buffers, large lookup tables, and general-purpose heap in Linux-capable SoCs. On resource-constrained microcontrollers (8-bit AVR, small PIC, most Cortex-M0/M0+ devices), SDRAM is rarely used; it becomes relevant mainly from mid-range Cortex-M4/M7 parts upward (STM32F4/F7/H7, i.MX RT series) and on application-class SoCs (NXP i.MX, Microchip SAMA5, Allwinner, Rockchip).
Interfacing SDRAM requires attention to several electrical and timing details. The bus is wide (typically 8, 16, or 32 bits of data, though wider configurations exist), runs at frequencies ranging from ~66 MHz for legacy SDR SDRAM to several hundred MHz for DDR3/DDR4, and demands careful PCB layout with matched trace lengths, controlled impedance, and proper termination. On DDR variants, setup/hold windows can be very tight -- often in the range of hundreds of picoseconds or less depending on speed grade and generation -- making simulation and post-layout signal integrity analysis important steps before first silicon, reducing costly board respins.
SDRAM operation involves explicit commands: PRECHARGE, ACTIVATE (row open), READ/WRITE (column access), and AUTO-REFRESH. The memory controller -- either a dedicated peripheral like the STM32H7's FMC/SDRAM controller or an external FPGA/CPLD -- issues these commands and must schedule AUTO-REFRESH at the rate specified in the datasheet (typically every 64 ms per row, totaling thousands of refresh cycles per second). Forgetting to configure refresh, or configuring it too slowly, causes silent data corruption -- reads appear to succeed but return stale or garbage values.
Initialization latency is a common gotcha: SDRAM requires a specific power-on initialization sequence (typically a 100-200 us pause, followed by PRECHARGE ALL, multiple AUTO-REFRESH cycles, and a LOAD MODE REGISTER command) before it accepts normal read/write operations. Skipping or abbreviating this sequence results in unreliable behavior that may not manifest until temperature or supply voltage varies.
Frequently asked
What is the difference between SDR SDRAM, DDR, DDR2, DDR3, and DDR4?
SDR (single data rate) SDRAM transfers data once per clock cycle.
DDR (double data rate) transfers on both rising and falling edges, doubling effective bandwidth at the same clock frequency. DDR2, DDR3, and DDR4 each successive generation raises the I/O clock multiplier relative to the core clock, lowers supply voltage (from 2.5 V for DDR down to 1.2 V for DDR4), and tightens timing margins. Many
MCU-class SDRAM controllers (STM32 FMC, NXP SEMC, i.MX RT) support SDR SDRAM or LPDDR/DDR3L; full DDR4 is more commonly found on application-processor SoCs with a dedicated PHY, though the support matrix varies by MCU family and external PHY availability.
How does SDRAM differ from SRAM, and when should I choose one over the other?
SRAM uses flip-flop-based cells that hold state without refresh, offering lower
latency and simpler interfacing at the cost of much larger cell size and higher price per bit. SDRAM uses
capacitor-based cells that need refresh, adding controller complexity, but achieves far higher density and lower cost per megabyte. For small, latency-sensitive buffers (
stack, tightly coupled code, fast data structures), on-chip SRAM is preferred. For large external memory -- frame buffers, file caches, general
heap on Linux targets -- SDRAM is the practical choice.
What is the refresh requirement and what happens if it is not met?
SDRAM
capacitor cells leak charge over time. Most devices specify that all rows must be refreshed within a 64 ms window (some industrial/extended parts offer 128 ms). The memory controller must issue AUTO-REFRESH commands at the required interval -- derived from the device's row count and the refresh window, typically resulting in a refresh command every few microseconds, though the exact interval varies by device. If refresh is missed, cell charge decays and stored data is lost. This can appear as intermittent read errors or system crashes that worsen at higher temperatures, since leakage increases with temperature.
What PCB layout concerns are most critical for SDRAM?
The most critical concerns are trace length matching (skew between clock, data, and address lines can violate setup/hold margins), controlled impedance (typically 50 ohm single-ended or 100 ohm differential for
DDR strobe pairs), and adequate power supply decoupling close to the SDRAM VDD and VDDQ pins. For DDR variants, fly-by topology with on-die termination is standard. Even for SDR SDRAM at 133 MHz, trace length mismatch beyond a few hundred mils can cause marginal behavior visible only under load or temperature stress.
Can I execute code directly from SDRAM on a microcontroller?
On MCUs with an external memory controller that maps SDRAM into the CPU address space -- such as the STM32H7 with FMC or the NXP i.MX RT with SEMC -- the CPU can fetch instructions from SDRAM. However, SDRAM
latency (row activation plus CAS latency, often 5-10 clock cycles per random access) is much higher than on-chip
flash or tightly coupled memory. Executing performance-critical or
interrupt-driven code from SDRAM without a
cache typically degrades throughput significantly. On Cortex-M7 parts with L1 I/D caches, caching SDRAM regions can recover most of the performance penalty for code with reasonable locality.
Differentiators vs similar concepts
SDRAM is often confused with
SRAM and with the broader
DRAM family. SRAM (Static
RAM) requires no refresh and has lower
latency but is far larger per bit -- it is used for on-chip caches and small on-chip buffers, not large external memories. Plain asynchronous DRAM (pre-SDRAM) used address multiplexing and separate RAS/CAS strobes without a synchronous clock, making it harder to pipeline; SDRAM added the clock to allow burst transfers and pipelining. Within SDRAM, the SDR vs.
DDR distinction is important: SDR SDRAM transfers once per cycle, while DDR and its successors (DDR2/3/4, LPDDR2/3/4) transfer on both clock edges and use progressively higher prefetch widths, lower voltages, and tighter tolerances. LPDDR (Low Power DDR) is a variant optimized for mobile and embedded use, with additional self-refresh power modes and a different pinout from standard DDR.
