ULPI (UTMI+ Low Pin Interface) is a standardized interface that connects a USB controller (host or device) to an external USB PHY over an 8-bit parallel bus, reducing the pin count compared to the full UTMI+ interface while preserving its logical functionality.
In practice
ULPI was defined by a group of USB silicon vendors (including Intel, SMSC, and others) to solve a practical board-level problem: the full UTMI+ interface between a USB MAC and PHY requires a large number of signals (often cited as 60 or more, depending on the variant), making it impractical for most SoC and FPGA designs. ULPI multiplexes data, control, and register access over an 8-bit bus clocked at 60 MHz, reducing the interface to roughly 12 signals in a typical implementation (data[7:0], clock, direction, next, stop, and reset, though exact signal names and optional pins can vary). This makes it feasible to add high-speed (480 Mbps) USB capability to an SoC or FPGA that lacks an integrated PHY by connecting an external ULPI PHY such as the Microchip USB3300, TUSB1210, or Mentor/Synopsys-compatible parts.
In FPGA-based designs, a ULPI PHY companion chip (for example, the SMSC USB3300 or TI TUSB1210 in a small QFN package) is a common pattern for adding USB 2.0 high-speed to devices like Xilinx Artix-7 or Intel Cyclone V boards. USB controller IP cores (such as those in Synopsys DesignWare or open-source cores like the ulpi_wrapper) expose a ULPI port that maps directly to these PHY chips. On SoCs that do integrate a USB PHY, the internal MAC-PHY interface may in some cases be ULPI-based, though vendors vary and many use proprietary or other internal buses; this detail is typically transparent to the firmware developer.
A key architectural point is that ULPI uses a single bidirectional 8-bit data bus with a turnaround protocol controlled by the DIR and NXT signals. The PHY drives the bus when DIR is high (PHY-to-link), and the link (MAC/controller) drives it when DIR is low. Register reads and writes to PHY configuration registers (e.g., setting the line state, enabling the pull-up for device mode, or reading vendor ID) are performed over this same bus using a defined command/data sequence. Firmware developers typically do not interact with this directly; it is handled by the USB controller hardware or IP.
One practical pitfall when using an external ULPI PHY is clock management: in a common arrangement, the PHY generates and outputs a 60 MHz reference clock on its CLK pin, and the USB MAC uses this as its clock source, though some designs may differ in how clocking is integrated. Board layout must keep this clock trace short and manage signal integrity to minimize timing issues. Power sequencing also matters; several ULPI PHY datasheets specify that VDD must ramp before or simultaneously with VBUS to avoid latch-up or undefined register states at startup.
Frequently asked
What is the difference between UTMI+ and ULPI?
UTMI+ (
USB 2.0 Transceiver Macrocell Interface Plus) is the full logical interface defined by USB-IF between a USB MAC and PHY; it requires 60 or more signals. ULPI is a compressed version of that interface using an 8-bit multiplexed bus at 60 MHz, reducing the physical pin count to roughly 12. The two are functionally equivalent from the MAC's perspective; ULPI simply serializes the wider UTMI+ bus over fewer pins.
Which external PHY chips implement ULPI?
Common ULPI PHY parts include the Microchip (formerly SMSC) USB3300 and USB3301, the Texas Instruments TUSB1210, and the Rohm BU33USB1. These support
USB 2.0 high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation. All expose a standard ULPI register set (vendor ID, product ID, function control, interface control, etc.) accessible over the ULPI bus.
Do I need to write ULPI driver code in firmware?
Typically no. The ULPI interface is handled entirely in hardware by the
USB MAC (whether on-chip or as
FPGA IP). The MAC translates USB protocol activity into ULPI bus transactions automatically. Firmware interacts with the USB controller at a higher level through its own register interface or a USB
stack. The only firmware-visible effect of ULPI is occasionally needing to configure PHY
registers (e.g., VBUS sensing mode or charge pump settings) through the MAC's PHY access register, which some USB stacks expose as an initialization step.
Can ULPI support USB OTG?
Yes. The ULPI specification includes
registers and signaling for OTG functions, including VBUS control, ID pin sensing, and session request protocol (SRP) support. PHY chips like the USB3300 and TUSB1210 expose OTG control registers accessible over the ULPI bus, and
USB MAC cores that implement OTG use these to manage role switching between host and device.
Is ULPI limited to USB 2.0?
Yes, in its current form. ULPI was designed specifically for
USB 2.0 (up to 480 Mbps high-speed). USB 3.x SuperSpeed uses a separate PHY interface standard (PIPE) and a physically different transceiver architecture. Some USB 3.x parts integrate a USB 2.0 ULPI PHY alongside a SuperSpeed PIPE PHY, but the ULPI portion handles only the USB 2.0 signaling.
Differentiators vs similar concepts
ULPI is often confused with UTMI+ itself, or with HSIC (High-Speed Inter-Chip), another pin-reduced
USB 2.0 PHY interface. The key distinction is that HSIC replaces the full analog USB PHY with a 2-wire (STROBE/DATA) differential interface for chip-to-chip connections on the same PCB, operating at 480 Mbps without a standard USB connector. ULPI, by contrast, interfaces to a full USB PHY that drives a standard D+/D- bus and supports all three USB 2.0 speeds. ULPI is for connecting a MAC to a standalone transceiver PHY; HSIC is for direct chip-to-chip USB links with no external connector.
