Von Neumann architecture is a computer design model in which program instructions and data share the same memory space and are accessed over a common bus. It is the basis for the vast majority of general-purpose processors and most MCUs in use today.
In practice
On von Neumann MCUs, a single address space holds both the executable code and runtime data. The processor fetches instructions and reads or writes data over the same bus (or through a shared interconnect), meaning the two operations cannot occur simultaneously at the memory level in a strict von Neumann implementation — though in practice many embedded CPUs overlap instruction fetch and data access through internal Harvard-like structures, caches, or prefetch buffers. This shared-address-space organization is the defining structural trait that separates von Neumann from Harvard architecture. Most 32-bit MCUs — including ARM Cortex-M devices such as the STM32 and nRF52 families — present a unified address map at the system level, though they are more precisely described as modified Harvard: they use separate internal instruction and data buses for performance while exposing a single address space to software.
The shared-bus nature introduces what is commonly called the von Neumann bottleneck: peak throughput is limited because instruction fetches and data accesses compete for the same bandwidth. In practice this matters most when running code from slower external memory or when the memory bus is heavily loaded by both DMA and CPU activity. For code executing from tightly coupled on-chip flash or SRAM, the bottleneck is often masked by caches, prefetch buffers, or wide bus widths.
One practical consequence for embedded developers is that von Neumann systems allow code to be generated, written into RAM, and executed at runtime. This makes techniques like field-patching firmware functions in RAM, self-modifying code, and certain bootloader strategies straightforward to implement, since there is no hardware-enforced separation between the code and data regions. Whether those techniques are safe or advisable is a different question, but the architecture does not prohibit them at the hardware level.
Security is an increasing concern. Because instructions and data share the same address space, a buffer overflow or a runaway pointer can corrupt or overwrite code. Many modern von Neumann MCUs add software-configurable memory protection (MPU, where available on the specific core and device) or execute-never (XN) region attributes to compensate, but these are layered protections rather than an inherent architectural guarantee.
Frequently asked
What is the von Neumann bottleneck?
The von Neumann bottleneck is the throughput ceiling created when instructions and data compete for the same memory bus. The CPU cannot simultaneously fetch an instruction and read or write data in the same bus cycle. On-chip caches, wide buses, and prefetch buffers reduce the practical impact, but the constraint is fundamental to the architecture.
Most Cortex-M datasheets describe separate I-Bus and D-Bus. Does that make them Harvard, not von Neumann?
It makes them a hybrid, commonly called modified Harvard. The core internally uses separate buses to fetch instructions and access data in parallel, which improves performance. However, the system-level address map is unified: code and data share one address space,
RAM can hold executable code, and a peripheral can appear in the same map alongside
flash. Literature varies on the classification — some sources describe Cortex-M devices as von Neumann-like at the system level, while others emphasize the modified Harvard label — and the internal bus split is a genuine architectural distinction rather than a minor implementation detail.
Can I execute code from RAM on a von Neumann MCU?
Yes, and this is one of the practical advantages over a strict Harvard design. Because code and data occupy the same address space, you can copy a function into
SRAM and branch to it. This is commonly used for routines that must run while
flash is being erased or reprogrammed, since many flash controllers require the CPU to execute from a different memory during erase or write operations. Cortex-M devices, for example, support this via
linker scripts that place specific functions in the .ramfunc section.
How does von Neumann architecture relate to security vulnerabilities on embedded targets?
Shared instruction and data memory means malicious or corrupted data can potentially be interpreted as executable code.
Stack-based buffer overflows that overwrite return addresses are a classic example. Mitigations layered on top of the architecture include MPU-enforced no-execute regions (available on Cortex-M3 and later), stack canaries, and address-space layout randomization. These are software or peripheral-level safeguards, not properties of the von Neumann model itself.
Is the original 6502 a von Neumann processor?
Yes. The MOS Technology 6502 uses a single unified address space of 64 KB for both program code and data, which is the hallmark of von Neumann organization. This design was discussed historically in 'Development of the MOS Technology 6502: A Historical Perspective' on EmbeddedRelated, and the shared address space was a deliberate simplification that reduced pin count and chip area.
Differentiators vs similar concepts
Von Neumann architecture is most often contrasted with
Harvard architecture, which uses physically separate memory spaces and buses for instructions and data. A strict Harvard design (common in many 8-bit PIC and AVR MCUs) cannot execute code from data
RAM and cannot use a pointer to read program memory through the normal data path. Most modern 32-bit MCUs are modified Harvard at the core level (separate internal I/D buses) but von Neumann at the system level (unified address map), which blurs the boundary. The key distinguishing question is whether the processor presents a single unified address space to software: if yes, it is classified as von Neumann or modified Harvard; if the programmer must use special instructions or address spaces to access program memory, it leans toward strict Harvard.
