PLL enable with D-Bug 12 BDM?

Started by Sam Laur in 68HC1214 years ago 6 replies

I've had some problems recently while trying to debug my program, and enabling the PLL. What I'm doing is this: // PLL init ...

I've had some problems recently while trying to debug my program, and enabling the PLL. What I'm doing is this: // PLL init REFDV = 2; SYNR = 0; while (BIT(CRGFLG,LOCK) == 0); SET(CLKSEL,PLLSEL); // Wait until PLL locked, then select PLL clk


code warrior clocking PLL

Started by Dr Stewart Prince in 68HC1212 years ago 1 reply

I have a question about the timing inside of Codewarrior: Does CW emulate the PLL and the timing signals generated by it? In other works, ...

I have a question about the timing inside of Codewarrior: Does CW emulate the PLL and the timing signals generated by it? In other works, If I have a 1Mhz crystal used to generate the E and X clk frequencies, then later on in I start the PLL at a different frequency, does CW automatically change the clocking frequencies to account for the PLL? Stewart


PLL - how to tie signals if not used

Started by blewis999 in 68HC1212 years ago 4 replies

I seem to remember in the doc set or an appnote somewhere that if the pll was not being used, one of the signals should be tied (to Vcc ? or...

I seem to remember in the doc set or an appnote somewhere that if the pll was not being used, one of the signals should be tied (to Vcc ? or gnd?). But I can't find where this was. We have a need to disable the pll because of an error in the pcb layout and need to remove the components, can someone suggest the best practise please. Thanks in advance Robert Lewis


DG256B PLL Resync

Started by peter_lingier in 68HC1213 years ago

Hello All, I'm busy with a HCS12 DG256B. I have this PLL problem I would like to discuss about. I'm using the P&E...

Hello All, I'm busy with a HCS12 DG256B. I have this PLL problem I would like to discuss about. I'm using the P&E programming and debugging tools. When I step trough my code in debug mode, I put on a certain moment the PLLSEL bit on one. My PLL is adjusted o


XFC Loopfilter C and R values

Started by Adrian Vos in 68HC1215 years ago 2 replies

Hi All, Is anyone able to help me out with the setting of the Capacitor/resistor values for the PLL loop filter (going to the...

Hi All, Is anyone able to help me out with the setting of the Capacitor/resistor values for the PLL loop filter (going to the XFC pin) on the S12DP256. I am using a 4MHz crystal, and plan to use the PLL to generate the max bus frequency of 25MHz (50MHz PLL output). To d


PLL Internal ref clock selection

Started by vvibin2003 in 68HC1214 years ago 1 reply

Hi all, Could any one explain me the criteria to select the value of PLL Internal clock (REFCLOCK) which is used for the REFDIV ...

Hi all, Could any one explain me the criteria to select the value of PLL Internal clock (REFCLOCK) which is used for the REFDIV value calculation while setting up the PLL. REFDIV = ((OSCCLOCK)/(REFCLOCK)) - 1


PLL doesn't run

Started by Anonymous in 68HC1213 years ago 3 replies

Hello ! I've problem with PLL on my board : it refuses to run. On a other board, PLL runs OK. The cpu core connecting (board)...

Hello ! I've problem with PLL on my board : it refuses to run. On a other board, PLL runs OK. The cpu core connecting (board) is the same on the two boards (obtained by copy/paste) I stay indefinitely in the "while" loop, that means LOCK bit never go to


9s12d64 -Trouble with PLL and filter

Started by imtiyazfmn in 68HC126 years ago 5 replies

Hello, I am using 5 mhz CLK in source and i need 1.25 mhz Bus clk so i used internal PLL for that ,i have done following thing for that...

Hello, I am using 5 mhz CLK in source and i need 1.25 mhz Bus clk so i used internal PLL for that ,i have done following thing for that is 1)SYNR=00; 2)REFDIV=03; EX CODE IS: /*PLLCTL=0xB1; /*PLL off */ /*goto PLL_BYPASS; */ CLKSEL=0x00; REFDV=03; /* BUSCLK=5MHZ*(0+1)/(3+1) */ SYNR=00; Lock_loop: for (i=0; i < 30000;i++){} /* Delay some time ... */ bit=CRGFLG & LOCK; if(bit ==0x00)


PLL Freq range

Started by imtiyazfmn in 68HC126 years ago 1 reply

Hello, I am using 5 mhz clk source for uC 9s12d64 and i wanted to set bus frequency = 1.25 mhz , is it possible by using PLL ? for your...

Hello, I am using 5 mhz clk source for uC 9s12d64 and i wanted to set bus frequency = 1.25 mhz , is it possible by using PLL ? for your information i have read in data sheet that PLL Locking range is from 8 mhz to 50 mhz for FVCO so for my project if my clk source is at 5mhz then FVCO should at 2.5 mhz. ------------------------------------


Three component PLL network useless?

Started by Oliver Betz in 68HC1215 years ago 9 replies

Hi All, anybody out there with some knowledge of the D60(A) PLL behaviour? I think the three component (R+C)||C network is...

Hi All, anybody out there with some knowledge of the D60(A) PLL behaviour? I think the three component (R+C)||C network is not better than a single capacitor. Maybe even worse! It would be great to read some other opinion on this topic. I compared a


trouble in BDM debugger when PLL gets ON- HC12

Started by imtiyazfmn in 68HC126 years ago 1 reply

Hello, I am using BDM debugger for my 9S12d64 device normally it works fine but when i am going to switch internal clock to PLL clock it gets...

Hello, I am using BDM debugger for my 9S12d64 device normally it works fine but when i am going to switch internal clock to PLL clock it gets halt and gets disconnected so please give your suggestions for this. Thanks, Imtiyaz ------------------------------------


trouble with PLL on the HC12

Started by Chris in 68HC126 years ago 13 replies

Hello; I am using an ICC12 compiler and NOICE debugger with a USB pod with an HC12 128kB chip running with a 16MHz crystal. My problem is that...

Hello; I am using an ICC12 compiler and NOICE debugger with a USB pod with an HC12 128kB chip running with a 16MHz crystal. My problem is that when I try to set the PLL up for about 40MHz, the code does not seem to work in the way it should and I can't get a LOCK - or even a TRACK signal. I have to turn off the PLLSEL bit before trying to set up the mult and divide registers and turning the...


Re: AN2153 Boot loader note about bug in initial silicon

Started by Gordon Doughman in 68HC1214 years ago 2 replies

Rod/Doron, This problem was only present in the 0K36N mask set. Regards, Gordon Doron Fael wrote: >Rod, > ...

Rod/Doron, This problem was only present in the 0K36N mask set. Regards, Gordon Doron Fael wrote: >Rod, > >The extra NOPs are indeed required for the PLL. > >After changing the PLL registers of the HCS12, there


HCS12X PLL

Started by Michael Burgess in 68HC1212 years ago 2 replies

I am using a DEMO9S12XDT512 Eval Board. This board is equipped with a 4.000MHz. crystal. I'm trying to reconfigure the processor to use the...

I am using a DEMO9S12XDT512 Eval Board. This board is equipped with a 4.000MHz. crystal. I'm trying to reconfigure the processor to use the internal PLL and bump up the frequency. After configuring the appropriate registers, and loading the program, the processor still runs at the 4.000MHz rate. However, if I single step the writing of the SYNR register, then it runs at my desired freq...


oscillator circuitry

Started by Robert Imhoff in 68HC1214 years ago 2 replies

I wanted to ask the hardware specialists if one should use special high-frequency capacitors for the PLL and quartz circuit on the...

I wanted to ask the hardware specialists if one should use special high-frequency capacitors for the PLL and quartz circuit on the HCS12 or if multilayer "C0G" ceramic capacitors are ok? (the crystal is 4 MHz and the PLL should run at 24 MHz, with a 9S12DT256C or similar, usin


Promlem with the MC9S12D64's PLL with USB Multilink

Started by shcaoyh in 68HC1212 years ago 1 reply

I use the P&E USB HCS08/HCS12 Multilink as the development tool, the target is the 80 pins MC9S12D64. This board is a simple circuit, I...

I use the P&E USB HCS08/HCS12 Multilink as the development tool, the target is the 80 pins MC9S12D64. This board is a simple circuit, I use a 16MHz quartz crystal with the Colpitts configuration. With the REFDV=1 and the SYNR=2, the CPU bus frequence is 24MHz. The PLL initialization application have a delay before switch the system clock


HCS12D PLL Woes

Started by Jonathan Masters in 68HC1210 years ago 4 replies

Hi all, I am just upgrading a product and will for only the second time use the PLL. In the first instance, the clock was only multiplied up...

Hi all, I am just upgrading a product and will for only the second time use the PLL. In the first instance, the clock was only multiplied up from 8MHz to 12.5MHz and I haven't experienced any problems with that product. In the current instance the bus clock is being multiplied up from 8MHz to 25MHz. Now I have all sorts of problems with the (PEMICRO) BDM pods. (Yes I have set CLKSW a...


How much clock variance can BDM's tolerate?

Started by tonalbuilder2002 in 68HC1214 years ago 2 replies

I'm working on a 9s12 project that requires an accurate 115200 baud SCI. I want to run the 9s12 PLL at 22.1182 mHz, which gives a ...

I'm working on a 9s12 project that requires an accurate 115200 baud SCI. I want to run the 9s12 PLL at 22.1182 mHz, which gives a perfect 115200 baud. One possibility is to use a standard xtal frequency of 3.686 mHz, and PLL it up to 22.118 mHz. But is 3.686 mHz too far off


PLL filter values

Started by Jordi Costa in 68HC1214 years ago 2 replies

We are making a development using HCS12 and evaluation board MM68KIT912DP256. Oscillator is 16 MHz external and clock frequency is...

We are making a development using HCS12 and evaluation board MM68KIT912DP256. Oscillator is 16 MHz external and clock frequency is set to 50 MHz. Now we are going to design our own board and set PLL filter values. C13 and C14 capacitor values are not shown in evaluation board schematics while R2 is 4


A little more help

Started by the_oog6789 in 68HC1213 years ago 4 replies

Back again.. I been playing around with my new hcs12 and I've managed to set up some serial communication, played around...

Back again.. I been playing around with my new hcs12 and I've managed to set up some serial communication, played around with the PLL to increase the chips clock speed and used the RTI. What I'm stuck on at the moment is the external interrupts through P