How is a "processor" defined when considering requirements on developing a design? A project I am on is shoving software into HDL to design an...

How is a "processor" defined when considering requirements on developing a design? A project I am on is shoving software into HDL to design an FPGA which is being considered "hardware". I'm not fighting it because FPGAs are what I do. Board level design is a necessary evil to support the FPGA. If not for the desire to make approval easier the FPGA would not be on the board.

It's a while since I last looked at USB but I'm finding it difficult to source useful material to explain the data packet I get from a USB...

It's a while since I last looked at USB but I'm finding it difficult to source useful material to explain the data packet I get from a USB mouse. I have 3 mice I'm looking at for reference and to understand what I have to deal with. This is for a USB HID Host application running on a STM MCU. The only documentation I have is hid1_11.pdf which can be easily found and on page 71 this giv...

I know most processors have an instruction for division and certainly Forth includes division words. But how are they implemented? I am asking...

I know most processors have an instruction for division and certainly Forth includes division words. But how are they implemented? I am asking because I need to do a division in hardware in an FPGA. Are there processors that don't include a division instruction? Has anyone had to implement division using something other than a native CPU division instruction? I worked on a

It will be the first FPGA for me. What I want to do is not complex, I have done similar controllers (more complex really)numerous times using...

It will be the first FPGA for me. What I want to do is not complex, I have done similar controllers (more complex really)numerous times using logic parts, PLD, CPLD-s etc. I need to put together a display controller, to just do framebuffer memory -> display interface. Framebuffer memory will be some sort of DDRAM (DDR-which depending on the FPGA type), I'll be happy with a 1920x1080 framebuf

Wow! Designing in a group is strange. I'm helping with the design of a ventilator and it is a unique experience. We have people of many skill...

Wow! Designing in a group is strange. I'm helping with the design of a ventilator and it is a unique experience. We have people of many skill levels and talents, many I don't even know. The design seems to ping pong around based on the hot button issue of the day. They already have someone to do board level design, but he has a day job, so the work gets done a bit helter skelte

https://www.safetty.net/download/pont_pttes_2001.pdf Page 13 Note carefully what this means! There is a common misconception among the...

https://www.safetty.net/download/pont_pttes_2001.pdf Page 13 Note carefully what this means! There is a common misconception among the developers of embedded applications that interrupt events will never be lost. This simply is not true. If you have multiple sources of interrupts that may appear at ?random? time intervals, interrupt responses can be missed: indeed, where there are

Banned Content Warning The group you are attempting to view (comp.lang.forth) has been identified as containing spam, malware, or other...

Banned Content Warning The group you are attempting to view (comp.lang.forth) has been identified as containing spam, malware, or other malicious content. Content in this group is now limited to view-only mode for those with access. Group owners can request an appeal after they have taken steps to clean up potentially offensive content in the forum. For more information about content policies...

Hi good day; I want to see the possibility that if someone can help me generate a crc calculator from txt files, I have a text file, and the...

Hi good day; I want to see the possibility that if someone can help me generate a crc calculator from txt files, I have a text file, and the result of the crc by which it must be submitted I already have, but I don't know how to get to He actually has several files to do the test, but I couldn't get to those results; Can someone help me?

Maybe someone can help me out with this. I'm looking at the data sheet for the STM32L412xx trying to find details on the mapping of the input...

Maybe someone can help me out with this. I'm looking at the data sheet for the STM32L412xx trying to find details on the mapping of the input voltage range to the 12 bit code produced. It might appear that the Vref+ and Vref- pins define the exact range, but it seems unusual that it could be equal to the power rails. With Vref+ = 3.3V and Vref- = 0 volts does 0V on the input

Conceptually, memory (or a memory region) can be thought of as being readable, writeable or executable -- and any combination of these. ...

Conceptually, memory (or a memory region) can be thought of as being readable, writeable or executable -- and any combination of these. Hardware *may* enforce these protections -- to varying degrees. Usually, you opt to PREVENT some set of these operations (i.e., no write, no read, no execute). In many cases, this acts as an invariant -- "this is data; nothing should be mucking with it ...