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ATmeag128 8Mhz with Z85c30 SCC(zilog)

Started by sebastiankoo in comp.arch.embedded16 years ago 1 reply

Hello. I am coding to build-up SDLC(HDLC) in z85c30 with MCU, ATmega128. I am trying to build-up SDLC(HDLC) protocal H/w environment...

Hello. I am coding to build-up SDLC(HDLC) in z85c30 with MCU, ATmega128. I am trying to build-up SDLC(HDLC) protocal H/w environment is z85c30(CMOS) with 4.91520Mhz crystal for PCLK. Also, z85c30's D0~D7 is connected with MCU in un-multiplexed mode(=direct) communication specification is as below - 38.4kbps - NRZI mode - Response time: 50ms - Address: Lower=70...


Low cost - high performance ARM11 Android development kit

Started by leon20008 in comp.arch.embedded13 years ago 2 replies

We do believe that the Witech FL6410 is the perfection for Android-based smart-phones and tablet PCs. It has * a powerful Samsung S3C6410...

We do believe that the Witech FL6410 is the perfection for Android-based smart-phones and tablet PCs. It has * a powerful Samsung S3C6410 800MHz MCU, * 256MByte mDDR RAM and 1GByte NAND Flash providing you enough space for * storage and processing capacity; * Complete power management supporting sleep function; * 1.3 / 3.0MPixels CMOS camera support; * GPS, GPRS, 3G, WIFI support; * LC...


cmos image sensor master and slave mode

Started by bish in comp.arch.embedded15 years ago 4 replies

Hi everyone, I want to buy c3038 camera module that uses omnivision's ov6630 image sensor. I'm trying to make an interface for this camera in...

Hi everyone, I want to buy c3038 camera module that uses omnivision's ov6630 image sensor. I'm trying to make an interface for this camera in fpga to grab the frame. To have the complete control over the incoming data, I thought of using camera in slave mode. But there seems to be two problem with that: i) The ov6630 datasheet says that 'hsync' signal from master should be connected to c...


power consumption of integrated circuit in 0.13µm CMOS technology

Started by Geronimo Stempovski in comp.arch.embedded11 years ago 5 replies

Hi all, currently I am investigating a data sorting algorithm on hardware. The algorithm was implemented in VHDL and is currently running on...

Hi all, currently I am investigating a data sorting algorithm on hardware. The algorithm was implemented in VHDL and is currently running on a Xilinx Virtex-II Pro XC2VP70 - FF1704 FPGA. Power consumption is a crucial aspect in the target application. Therefore I made an analysis with the Xilinx Virtex-II Pro Web Power Tool (www.xilinx.com) and obtained satisfying results. Now I'd ...


3.3V CMOS processor driving a device with Vih higher than processor Voh?

Started by Dave Boland in comp.arch.embedded19 years ago 4 replies

I need to drive a 5 volt ADC (LTC1863) to be able to use a Vref of 4.096 volts. The Vih of the ADC is 2.4 volts. The processor is a 3.3 volt...

I need to drive a 5 volt ADC (LTC1863) to be able to use a Vref of 4.096 volts. The Vih of the ADC is 2.4 volts. The processor is a 3.3 volt xMOS with a Voh of 2.6 volts (measurements show it to be 3.1 volts with no load, but the processor spec. says 2.4 volts at 3.0 volts). So I have a 200 mV margin. Anyone done something like this, and how reliable is it? To get an idea of wha...


Strategy to recover from checksum errors?

Started by Juergen Marquardt in comp.arch.embedded20 years ago 5 replies

Hi, trying to find some strategy to recover from checksum errors of my enbedded systems SRAM. Hardware useable in my hardware is a)...

Hi, trying to find some strategy to recover from checksum errors of my enbedded systems SRAM. Hardware useable in my hardware is a) battery buffered static ram (SRAM, 128 kByte) and b) battery buffered static ram (so called CMOS ram in clock chip, some 10 bytes) and c) Compact Flash card (some MByte) It is relatively easy to find out a sram area having been currupted by calculating ...



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