ISSCC 2005, 6-10 Feb 2005 ( http://ps2.unisord.com/ ) Presentations: -A Streaming Processing Unit for a CELL Processor (STI) -The Design...

ISSCC 2005, 6-10 Feb 2005 ( http://ps2.unisord.com/ ) Presentations: -A Streaming Processing Unit for a CELL Processor (STI) -The Design and Implementation of a First-Generation CELL Processor (STI) -A Double-Precision Multiplier with Fine-Grained Clock Gating Support for a First-Generation CELL Processor (IBM) -A 4.8GHz Fully Pipelined Embedded SRAM in the Streaming Processor of a CELL...

Mobilygen develops low-power H.264 video compression ICs for mobile products. Our patented EVE (Enabling Video Everywhere) architecture combines...

Mobilygen develops low-power H.264 video compression ICs for mobile products. Our patented EVE (Enabling Video Everywhere) architecture combines data-driven media engines, an ultra-efficient memory controller, and hardware multithreading, each tuned specifically for mobile video applications. The result is extremely low-power ICs that run at very low clock rates and can utilize standard commo...

Hi, all. Hope I am in a right place with my question. I have a LPC2368-based custom board with Marvell switch 88E6171R installed. My problem...

Hi, all. Hope I am in a right place with my question. I have a LPC2368-based custom board with Marvell switch 88E6171R installed. My problem is related to management of the switch device via MDC/MDIO bus. The device's user's manual says that on one hand the device supports MDC frequency up to 20 MHz. On the other hand, it says, that minimum MDC clock cycle is 120 ns, i.e. 8.33 MHz. I di...

We have just released a new board MYD-JA5D4X based on atmel sama5d44. It is said that Compared to the previous Cortex-A5 SoC from Atmel, the...

We have just released a new board MYD-JA5D4X based on atmel sama5d44. It is said that Compared to the previous Cortex-A5 SoC from Atmel, the SAMA5D3, the SAMA5D4 brings a L2 cache, NEON, a slightly different clock tree, a hardware video decoder, and Trustzone support. The sama5d44 can support 720p hardware video decoder, that's true, the video display seems much better. http://ww

Question regarding PIC 18 series performance verses MSP430F149: Currently I'm using a TI MSP430F149 running at 12Mhz (overclocked) in a...

Question regarding PIC 18 series performance verses MSP430F149: Currently I'm using a TI MSP430F149 running at 12Mhz (overclocked) in a prototype. For various reasons I'm considering using a PIC 18Fxxx, but want to know before I bother porting the code/building hardware if the PIC running at a 10MHz instruction clock will give me similar performance to the MSP430 at 12Mhz. Here are some d...

I am working with ST micom and have some questions on SPI. I have asked on ST forum that I can see SCLK when micom is master and sending data,...

I am working with ST micom and have some questions on SPI. I have asked on ST forum that I can see SCLK when micom is master and sending data, but I can't when micom is master and receiving data. Then someone answered that I should send null data to active SCLK even when I want to receive data. Is this right method? And another question. When master micom is sending out clock, how micom can...

Hello all, I am in the process of selecting a processor. I have few queries related with the selection of a processor for embedded...

Hello all, I am in the process of selecting a processor. I have few queries related with the selection of a processor for embedded systems design . For selecting the correct processor to handle high rate of data, is there any mapping/logic between the processor clock speed and the rate in which the data enters the processor . That is, consider that the data comes in at the rate of 1Gbps in t...

Kernel hangs after the control is transferred U-Boot 1.1.3 (ppc83xx-20050315-dev) (Jun 29 2006 - 16:33:51) MPC83XX *** THIS IS AN ALPHA...

Kernel hangs after the control is transferred U-Boot 1.1.3 (ppc83xx-20050315-dev) (Jun 29 2006 - 16:33:51) MPC83XX *** THIS IS AN ALPHA VERSION OF UBOOT FOR 8325 *** Clock configuration: Coherent System Bus: 132 MHz Core: 264 MHz QE: 99 MHz Local Bus Controller: 132 MHz Local Bus: 16 MHz DDR: 264 MHz ...

I have seen the Write cylce time of EEPROM is in 'ms' ie., around 10ms. Why this time is so high while the RAM write cycle time is with in ...

I have seen the Write cylce time of EEPROM is in 'ms' ie., around 10ms. Why this time is so high while the RAM write cycle time is with in a clock cycle. -Muthu

Hello, I need some help to activate full stop mode in MAC7121: before I activated pseudo-stop mode, and it works fine. Now I need to activate...

Hello, I need some help to activate full stop mode in MAC7121: before I activated pseudo-stop mode, and it works fine. Now I need to activate full stop mode, but it doesn't work. This is the code: CRG.CLKSEL.B.PLLSEL = 0; // selected oscilator clock CRG.PLLCTL.B.PLLON = 0; // stop PLL MCM.MWCR.R=0x80; // activated wakeup on interrupt #ifdef FULL_STOP CRG.CLK...

Hello. I was wondering if someone can explain to me the relationship between the HCLK (AHB side) and PCLK (APB side) in an AMBA system. After...

Hello. I was wondering if someone can explain to me the relationship between the HCLK (AHB side) and PCLK (APB side) in an AMBA system. After the bridge, is the PCLK frequency the same as that of HCLK? How much slower is the APB side compared to the AHB side, or is it just at matter of the number of clock cycles required to perform the accesses? Do peripherals connected to the APB divid...

Hi, I'm building an embedded controller that uses the Dallas 89C420 ultra high speed micro with an external 32K SRAM. There's no...

Hi, I'm building an embedded controller that uses the Dallas 89C420 ultra high speed micro with an external 32K SRAM. There's no external program memory - I'm using the internal flash for that. Right now it works just fine at 15Mhz with a 74HC373 address latch and a 70ns SRAM, however I want to run in clock doubled mode at 30Mhz. For this I figure I'll need to use a 74F373 latch instead...

Hi, Guy's, I'm not sure if this is the best place to ask but, I am currently learning VHDL and am trying to design a RAM model with the...

Hi, Guy's, I'm not sure if this is the best place to ask but, I am currently learning VHDL and am trying to design a RAM model with the following spec: Inputs: A (3 bit address), D (4 bit data), Clock, plus control input(s) as required Output: Q (5 bit data) The design contains two units, a RAM (3 bit address, 4 bit data, separate data input and output) and an arithmetic unit (two 4-bi...

Hi, I received a couple of RCM 6750 Modules. At some I got the following errormessages: line 19 : WARNING SYSCONFIG.LIB : _DC_CLK_DBL_...

Hi, I received a couple of RCM 6750 Modules. At some I got the following errormessages: line 19 : WARNING SYSCONFIG.LIB : _DC_CLK_DBL_ should always be defined, but was not defined: line 20 : WARNING SYSCONFIG.LIB : Defined _DC_CLK_DBL_ to 0 (disabled clock doubler recommendation). line 27 : ERROR BOARDTYPES.LIB : No ID Block found on the target board. line 28 : ERROR BOARDTY...

Hi, I have a Beaglebone like board, which has CPU clock rate 800MHz. It runs a Linux. I find an audio project, which needs CPU power 200MIPS...

Hi, I have a Beaglebone like board, which has CPU clock rate 800MHz. It runs a Linux. I find an audio project, which needs CPU power 200MIPS for computing. The audio stream can tolerate some latency such as 10mS. To port this audio project to Linux needs some time and a lot of work to do. Now, I would like to know whether this 800MHz ARM Beaglebone board can run through this audio project. ...

Based on SDIO spec v3.0 I have some doubts. a. SDIO 2.0 can support 7 function in one card. And these 7 functions all share 1 CLK , 1 CMD and...

Based on SDIO spec v3.0 I have some doubts. a. SDIO 2.0 can support 7 function in one card. And these 7 functions all share 1 CLK , 1 CMD and 4 DAT lines ,right? b. SDIO 3.0 have a new feature that is embedded SDIO.It's "shared bus" feature. It used 7 CLK pin and 1 CMD and 4 DAT(8 is optional) lines for 7 functions,right? c. I wonder what different it is? Just only increase clock pins...

I am looking at a design which uses a PIC18F8520 whose USART is connected to a PC serial port running at a fairly high data rate. I am also...

I am looking at a design which uses a PIC18F8520 whose USART is connected to a PC serial port running at a fairly high data rate. I am also looking at the design of a serial port instantiated in an FPGA connected to the same data stream in an RS-485 network. Having to deal with the internal details of the FPGA "USART" makes me wonder about the internal details of the PIC USART. FOr instanc...

We are starting the wiki dedicated to W90P710 ARM SoC from Nuvoton. The W90P710 is a ARM7TDMI SoC features: 1. CPU clock up to 80 MHz. 2....

We are starting the wiki dedicated to W90P710 ARM SoC from Nuvoton. The W90P710 is a ARM7TDMI SoC features: 1. CPU clock up to 80 MHz. 2. LCD Controller that support STN and TFT LCD Displays (working fine with 640x480x16bit). 3. TV Encoder. 4. 10/100M Ethernet MAC Controller RMII only. 5. Four UARTs. 6. USB Host Controller 12Mbit Full Speed. 7. USB Device 12Mbit Full Speed. 8. ...

Hi, I have an fpga which is accessed from ARM as a memory-mapped device. A register in fpga is used to drive a I2C bus connected...

Hi, I have an fpga which is accessed from ARM as a memory-mapped device. A register in fpga is used to drive a I2C bus connected to a device . Two bits in the register represent clock and data lines of the bus. When I try to write into this register from ARM software as shown below, write is not happening. ARM is running at 48 Mhz. int* reg = 0x44400030; *reg = 0x3; T...

Hi, trying to find some strategy to recover from checksum errors of my enbedded systems SRAM. Hardware useable in my hardware is a)...

Hi, trying to find some strategy to recover from checksum errors of my enbedded systems SRAM. Hardware useable in my hardware is a) battery buffered static ram (SRAM, 128 kByte) and b) battery buffered static ram (so called CMOS ram in clock chip, some 10 bytes) and c) Compact Flash card (some MByte) It is relatively easy to find out a sram area having been currupted by calculating ...