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Timer reset on compare match ??

Started by Robert Bielik in comp.arch.embedded20 years ago 1 reply

Hi All, I'm sitting here with a H8S/2633F cpu and I'm setting up a 16 bit TPU for reset on compare match A (TGRA). The question is: When...

Hi All, I'm sitting here with a H8S/2633F cpu and I'm setting up a 16 bit TPU for reset on compare match A (TGRA). The question is: When exactly will the timer reset ? ON compare match, or the clock pulse after ?? I.e. if I set TGRA to 0x1234, what will the timer range be? A) 0x0000 - 0x1234 meaning that a loop will contain 0x1235 clock pulses B) 0x0000 - 0x1233 -> loop contains 0x1234


Journal Special Issue on Software Development for Multi-Core Computing Systems

Started by Sabri Pllana in comp.arch.embedded16 years ago

CALL FOR PAPERS Scientific Programming Journal Published by IOS Press Special Issue on Software Development for Multi-Core Computing...

CALL FOR PAPERS Scientific Programming Journal Published by IOS Press Special Issue on Software Development for Multi-Core Computing Systems AIMS AND SCOPE: The improvement of single-processor performance by increasing clock rate and instructions-per-clock number has reached its technological limits. Increasing instead the num


I2C vs SPI

Started by Joe G (Home) in comp.arch.embedded14 years ago 9 replies

Hi All, SPI is more simplistic in internal IC hardware design than I2c. If the SPI data bus receive garbage (spikes or noise) you can pull...

Hi All, SPI is more simplistic in internal IC hardware design than I2c. If the SPI data bus receive garbage (spikes or noise) you can pull the chip select high and start clocking the data in/out again. SPI has /CS chip select Clock Data out Data in I2C has Clock Data Question ======== If an I2C bus receives garbage, how does one tell a I2C receiver to "reset" and start...


MicroBlaze latencies

Started by 3.14 in comp.arch.embedded19 years ago 1 reply

In "Embedded System Tools Guide" on EDK6.2 say: ".... MicroBlaze requires 2 clock cycles to access on-chip Block RAM connected to the LMB...

In "Embedded System Tools Guide" on EDK6.2 say: ".... MicroBlaze requires 2 clock cycles to access on-chip Block RAM connected to the LMB for write and 2 clock cycles for read. On chip memory connected to the OPB bus requires 3 cycles for write and 4 cycles for read...." I don't understand, request latecies to BRAM = 1 tick. Request latecies to OPB (from timing waveforms) = 1 tick, if "Ac...


m68k-elf-objcopy does not convert .ELF to .BIN file

Started by KBG in comp.arch.embedded18 years ago 7 replies

Hi, .ELF to .BIN conversion is working for one set of source code , but it is not working with another set of code . I do the following...

Hi, .ELF to .BIN conversion is working for one set of source code , but it is not working with another set of code . I do the following for converting the .ELF to .BIN : "m68k-elf-objcopy -O binary clock.elf clock.bin". Does source code have any role in affecting the generation of .ELF to .BIN ? OR Does configuration settings of the compiler that generates the .ELF file ...


Real Time Clock

Started by David Evennou in comp.arch.embedded20 years ago 10 replies

I am looking for a RTC Chip, maybe with SPI for communications with 68HC908GP32. Any suggestions? TIA, David

I am looking for a RTC Chip, maybe with SPI for communications with 68HC908GP32. Any suggestions? TIA, David


OMAP 5912 and 5910 - MPU Clock/Reset/Power Mode Control Registers

Started by karthikbg in comp.arch.embedded17 years ago 1 reply

Hi, I have some queries based on the MPU Clock/Reset/Power Mode Control Registers of OMAP 5912 and 5910. Does the term "OMAP 3.2 hardware...

Hi, I have some queries based on the MPU Clock/Reset/Power Mode Control Registers of OMAP 5912 and 5910. Does the term "OMAP 3.2 hardware engine" mentioned in OMAP 5912 technical document refer to the term "DSP" mentioned in OMAP 5910 technical document. Pls find the snapshot of the info : In OMAP 5912 ============= ARM_RSTCT1 - MPU Reset Control 1 Register . This is a 32-bit ...


Flash mcu with SPI slave capable of 16MHz operation?

Started by Antti in comp.arch.embedded17 years ago 16 replies

I guess none available :( all seem limit to clock/4 or something but maybe I have missed some good part? Antti

I guess none available :( all seem limit to clock/4 or something but maybe I have missed some good part? Antti


microcontroller selection

Started by eeh in comp.arch.embedded18 years ago 7 replies

Hi, I want to select a 8 bit microcontroller which can be run under 3V and with 12MHz clock. Any choice?

Hi, I want to select a 8 bit microcontroller which can be run under 3V and with 12MHz clock. Any choice?


8051 architecture

Started by Anonymous in comp.arch.embedded18 years ago 45 replies

Why 8051 need 2 clock cycle for 1 system state?

Why 8051 need 2 clock cycle for 1 system state?


486 pll

Started by Anonymous in comp.arch.embedded19 years ago 2 replies

Does anyone know if the internall PLL on an Intel 80486 can be by-passed or disabled? I want to single step using an externally controlled...

Does anyone know if the internall PLL on an Intel 80486 can be by-passed or disabled? I want to single step using an externally controlled clock without the PLL. Thanks, Wayne


8253

Started by Pascal Garcia in comp.arch.embedded18 years ago 1 reply

Hi, sorry if this is off-topic, but reading the datasheet of the 8253, I don't understand the sentence concerning the mode 2 and 3 : "In...

Hi, sorry if this is off-topic, but reading the datasheet of the 8253, I don't understand the sentence concerning the mode 2 and 3 : "In modes 2 and 3, if a CLK source other than the system clock is used, GATE should be pulsed immediately following /WR of a new count value" can somebody help me ? pascal


quadrature encoder

Started by princekcs in comp.arch.embedded14 years ago 16 replies

why is it necessary to clock on rising and falling edge when reading a quadrature encoder? ...

why is it necessary to clock on rising and falling edge when reading a quadrature encoder? --------------------------------------- Posted through http://www.EmbeddedRelated.com


Micro with 5-6 independent UARTs?

Started by ElderUberGeek in comp.arch.embedded17 years ago 12 replies

Anyone know of a micro that has 5-6 UARTS that can each run a different baud rate? (meaning not the same clock). Oh, and a TCP stack would be...

Anyone know of a micro that has 5-6 UARTS that can each run a different baud rate? (meaning not the same clock). Oh, and a TCP stack would be nice also.... Thanks


87c520

Started by Angela & Gary in comp.arch.embedded19 years ago 1 reply

Simple question re: the serial port. I would like to clock the micro @ 25MHz. What serial port speeds would this support? Thanks in...

Simple question re: the serial port. I would like to clock the micro @ 25MHz. What serial port speeds would this support? Thanks in advance. Gary


TMDS to LVDS

Started by volucris in comp.arch.embedded15 years ago 3 replies

Hi folks, I need to convert TMDS to LVDS. Im sure someone has done this before, so rather than reinvent the wheel, I'd like to ask what chips...

Hi folks, I need to convert TMDS to LVDS. Im sure someone has done this before, so rather than reinvent the wheel, I'd like to ask what chips are suitable for this. I need to drive a panel with 3 data and one clock pair (so I assume 18 bit?) Thanks, -Ian


ST semi RTC M41T94

Started by Martin Griffith in comp.arch.embedded16 years ago 12 replies

I'm waiting for a couple of M41T94 real time clock chips to arrive, so I'm scribbling some 8052 C code in advance. It's an SPI ic. Any gotchas...

I'm waiting for a couple of M41T94 real time clock chips to arrive, so I'm scribbling some 8052 C code in advance. It's an SPI ic. Any gotchas on this RTC? Thanks martin


how to write a simulator for a processor

Started by Master in comp.arch.embedded20 years ago 4 replies

i want programming details abt writing a processor Simulator in c language.. simulating a interrupt,clock ,bus register etc.. please mail...

i want programming details abt writing a processor Simulator in c language.. simulating a interrupt,clock ,bus register etc.. please mail me at bsvijayan@yahoo.com thank u buddy..


Compiling code

Started by Mike Burch in comp.arch.embedded16 years ago 15 replies

Hello fella's I know I am completely out of my league with this question but I have to ask anyway. Be gentle. :-) I have built this clock...

Hello fella's I know I am completely out of my league with this question but I have to ask anyway. Be gentle. :-) I have built this clock because it is really cool! and it is completed up to the point of programming it. It uses 3 pic18f252 micro controllers. 1 controller is a master and 2 respond as slaves. I don't know how to do this. I think it would be like flash programming a bio...


Start-up Xilkernel on Microblaze

Started by Yannick in comp.arch.embedded16 years ago 1 reply

Hi, How many long Xilkernel take to startup with microblaze (System Clock : 50 MHz). On my design, the Microblaze need more than 30 second to...

Hi, How many long Xilkernel take to startup with microblaze (System Clock : 50 MHz). On my design, the Microblaze need more than 30 second to create the first thread after xil_kernel_main(). Regards, Yannick



The 2024 Embedded Online Conference