hello, I am working on a cypress chip. I want the communication between endpoints and host to work on external clock. Is it possible for chip to...

hello, I am working on a cypress chip. I want the communication between endpoints and host to work on external clock. Is it possible for chip to work on external clock without being in Slave FIFO or GPIF mode? Regards Sanika

Setup - Cypress Development Board, with FX1 - out bulk transfer on EP6 - double buffering - ports I/O (IFCONFIG:0.1 = 00b) Firmware is...

Setup - Cypress Development Board, with FX1 - out bulk transfer on EP6 - double buffering - ports I/O (IFCONFIG:0.1 = 00b) Firmware is based upon the samplecode 'bulkloop' supplied with the Development Board. Extract from ISR_EP6inout: { .... EP6BCL = 64; // write anything to BC to allow EP to be written to again EZUSB_IRQ_CLEAR(); // Clear US...

Guys, I am working with a Cypress EZ-USB FX2 prototyping board connected to an Omnivision camera chip that spits out data far faster than...

Guys, I am working with a Cypress EZ-USB FX2 prototyping board connected to an Omnivision camera chip that spits out data far faster than the GPIF's Endpoint buffers are programmed to handle. The Keil uVision compiler is used for the firmware and libusb 0.1.12.0 for enumerating the USB devices at the PC end. I am using Control Requests, (or Vendor Requests in GPIF parlance) to co...

I just got my brand new EZUSB dev kit from Cypress which comes with an eval version of the Keil compiler and many handy examples which I...

I just got my brand new EZUSB dev kit from Cypress which comes with an eval version of the Keil compiler and many handy examples which I got running in no time flat with the Keil tools. My question is regarding the SDCC compiler. Since SDCC likely does not directly support all of the features of the FX2LP can anyone tell me the limitations for its use on this particular platform? I'm havi...

Any Cypress FX2 (USB) gurus out there? I have one of these devices on an FPGA board (Digilent Nexys), which only provides an 8-bit external...

Any Cypress FX2 (USB) gurus out there? I have one of these devices on an FPGA board (Digilent Nexys), which only provides an 8-bit external datapath instead of 16 bits. I'd like to stream substantially wider words (32, maybe 48 bit) to a PC application. Could anyone provide some clarity on what mechansims exist to synchronize the byte-wide data to application word boundries? Is there ...

(Xposted to c.a.e because we've been talking about these adapters there recently). I'm trying to use a Cypress-based USB-serial adapter to...

(Xposted to c.a.e because we've been talking about these adapters there recently). I'm trying to use a Cypress-based USB-serial adapter to connect an 8-bit embedded system (http://www.larwe.com/technical/current.html) to a Linux-based computer. Actually, I want to get it working on PPC Linux running on an MPC8241 but as a first step, I'm trying to get it to work on a regular PC. I upgra...

Cypress cover BOTH bases, in a move that has to get everyone's attention ! - Single clock 8051 16/32/64KF, up to 8KR, with up to 67MHz...

Cypress cover BOTH bases, in a move that has to get everyone's attention ! - Single clock 8051 16/32/64KF, up to 8KR, with up to 67MHz operation, and 120 part numbers Wide 1.7-5.5V operation.. LCD drive, 0.5V boost regulator... 0.1% voltage reference (14 ppm/=B0C) optional 24bx24b MAC - Cortex parts are 32K-256KF, and up to 64KRam, and 5.5V IO's well... (but no 32 bit timers?) Choic...

Hi all, I am using the Cypress FX2 to interface an FPGA to a PC via an USB2.0 link. The FX2 was configured to provide 4 bulk endpoints (+...

Hi all, I am using the Cypress FX2 to interface an FPGA to a PC via an USB2.0 link. The FX2 was configured to provide 4 bulk endpoints (+ synchronous FIFOs). Each bulk EP (2,4,6,8) is 512 byte long and is double buffered. All seems to work quite fine, but when a FIFO get full (i.e. the PC send more than 512 bytes) the EP does not take data any more, even if the FPGA empty the FIFO! The end...

Hi I am working on cypress chip CY68013A. I have configured the EP2 as Bulk endpoint. Endpt 2 FIFO -- 1024 byte Quad buffered , AUTOIN...

Hi I am working on cypress chip CY68013A. I have configured the EP2 as Bulk endpoint. Endpt 2 FIFO -- 1024 byte Quad buffered , AUTOIN enabled , SYNCHRONOUS mode. it is in SLAVE FIFO Mode receiving VIDEO data in EP2FIFO from a external master. I have programmed the EP2AUTOINLEN reg with value 512. The host application requests 65536 chunks of data.This works fine and i am able to s...

Hello, can someone tell me if there is a newer / improved version of ezusb.sys then version 1.1 which can be downloaded from cypress website...

Hello, can someone tell me if there is a newer / improved version of ezusb.sys then version 1.1 which can be downloaded from cypress website ? I saw the latest change was in september 2001. I googled around and read, that on http://www.devicedriver.com/ they write, you shouldn't use it for production because of bugs. Is this still valid today or were the mentioned bugs removed from c...

The answer didn't leap out at me from the data sheet, so... I'm working on a Cypress-FX2 based board, and the driver has decided to bring the...

The answer didn't leap out at me from the data sheet, so... I'm working on a Cypress-FX2 based board, and the driver has decided to bring the link up in full-speed mode rather than high-speed mode. Can anyone offer some pointers on how to force it to high-speed? The port does work at 4800Mbps, But I've never seen it do that with this FX2. TIA, G.

Cypress technical support has been really horrible, I hope someone here can help. I have a program for the FX2LP part. It runs fine when...

Cypress technical support has been really horrible, I hope someone here can help. I have a program for the FX2LP part. It runs fine when loaded with the Keil debug monitor, but does not run when loaded via CyConsole, or loaded into EEPROM. For the EEPROM, I'm using this command line: hex2bix -i -c 0x00 -f 0xC2 -o test.iic test.hex I have looked at the EEPROM image in the prom burn...

Hi, Banging my head against this silly problem when I could be out enjoying the rain. I cannot see what I am doing wrong. I've...

Hi, Banging my head against this silly problem when I could be out enjoying the rain. I cannot see what I am doing wrong. I've reduced it as far as possible, but it is still not clear. I have a simple loopback connection on UART1 (I've even reduced my code down so it will fit and run on the FX2 DK board). In Mode 1 the loopback works fine. I send "ABCD" and I receive ...

We have developed data acquisition system which uses Cypress FX2 as the USB 2.0 interface. State machine for control and conversion of data...

We have developed data acquisition system which uses Cypress FX2 as the USB 2.0 interface. State machine for control and conversion of data between AD converters and FX2 is implemented using Xilinx Spartan 2 FPGA. The problem is that with higher data rates (up to 25 Mbit/s) we experience FX2 internal FIFO stalls and missing data on the receiving side. Small FIFO implemented inside FPGA d...

Hi. I'm just starting to work with the Cypress EZ-USB FX2 chip (56 pin version), and the port pins are causing me trouble. I can't get...

Hi. I'm just starting to work with the Cypress EZ-USB FX2 chip (56 pin version), and the port pins are causing me trouble. I can't get them to output anything. My code is based on the a3load example. I use the EZ-USB Control Panel to load my code into the chip. To verify the build and load procedure, I added an extra vendor request code. My code executes and returns a "hello world" ...

Hi, I am new in FPGA and FX2 UC. I am looking for a good development board including xilinx FPGA and cyress Fx2 uc. I want to learn how to...

Hi, I am new in FPGA and FX2 UC. I am looking for a good development board including xilinx FPGA and cyress Fx2 uc. I want to learn how to program FPGA and FX2 uc. I went to several websites( usbp, Gnuradio, opal kelly, digilent...). They provide good development boards, but not all source codes open and no good tutorial written. Is any one know a good tutorial for Cypress FX2 uc + Xilinx F...

Hi, I have the Cypress FX2LP development kit, and according to the manual, I can select either large EEPROM(Microchip 24LC128) for simulation...

Hi, I have the Cypress FX2LP development kit, and according to the manual, I can select either large EEPROM(Microchip 24LC128) for simulation or small EEPROM(Microchip 24LC00) for debugging. Since I'm still in my development stage, I'm debugging the firmware, so I'm choosing small EEPROM. The problem is that I wish to address another I2C EEPROM chip in my firmware, a Microchip 24AA08. Acco...

Has anybody had any problems with the Cypress 811HS USB Host chip? I am having some strange stability problems. Sometimes I reboot, the chip...

Has anybody had any problems with the Cypress 811HS USB Host chip? I am having some strange stability problems. Sometimes I reboot, the chip would work perfectly. Other times (80% of times), when I reboot the chip, I can successfully write to a memory area on chip and read the same data back out. However, if I try to read and write to the control registers, I get garbage. The strange ...

Is there an easy software way to remove the vid/pid from the EEPROM and ge back to the initial Cypress one? Thanks Eric This...

Is there an easy software way to remove the vid/pid from the EEPROM and ge back to the initial Cypress one? Thanks Eric This message was sent using the comp.arch.embedded web interface o www.EmbeddedRelated.com