PC/104 plus bus communication with FPGA using Xilinx IPCore

Started by awa in comp.arch.embedded13 years ago 2 replies

Hi, I was wondering if anyone has ever use FPGA to communicate with another board that use PC/104 plus bus as the interface? To give a better...

Hi, I was wondering if anyone has ever use FPGA to communicate with another board that use PC/104 plus bus as the interface? To give a better view, I have one firewire board that uses a PCI-to-1394 host chip and another board that has an FPGA on it. I would like to control the firewire by using the FPGA. Does anyone has any suggestion on how to do this? I've tried using Xilinx PCi IPCor...


Ann: A new FPGA beginner's Video guide

Started by Tony Burch in comp.arch.embedded12 years ago

Hi all, I have just released a new online Video guide called "The BurchED Getting Started with Xilinx FPGAs Video Guide"...

Hi all, I have just released a new online Video guide called "The BurchED Getting Started with Xilinx FPGAs Video Guide" http://www.BurchED.com It is an easy step-by-step guide for FPGA beginners. I go all the way through from "What is an FPGA?" right up to compiling designs and downloading to your FPGA board There's a Free Membership area where you can watch some videos for free. ...


FPGA for hobbyist ??

Started by kunil in comp.arch.embedded15 years ago 6 replies

Just wondering, does hobbyist with fund less than USD200/month could afford playing with FPGA ? Is there any link that I can read about it ?...

Just wondering, does hobbyist with fund less than USD200/month could afford playing with FPGA ? Is there any link that I can read about it ? (since looks like every FPGA developer is belonging in big company and universities). I want to know what kind of tools that I need (like the compiler, development board, debugger, etc). Thus, is there any link to cheap version of it :p (I've rea...


ChipHit ASIC, FPGA, EDA Search Engine

Started by ted in comp.arch.embedded13 years ago

Hi, I debated putting this announcement here, however, if you are doing ASIC, or FPGA embedded design, this might be of help. I recently...

Hi, I debated putting this announcement here, however, if you are doing ASIC, or FPGA embedded design, this might be of help. I recently created a Google custom search engine called ChipHit at http://www.chiphit.com. Please take a look and provide suggestions. I spend many hours a day searching the internet for ASIC, FPGA, and EDA tool topics as I am ASIC/FPGA applications engineer. F...


Newby Getting started with FPGA

Started by Anonymous in comp.arch.embedded15 years ago 20 replies

I am new to the FPGA and I want to learn by small experiments. Can some FPGA experts tell me what is the easiest and least expensive way of...

I am new to the FPGA and I want to learn by small experiments. Can some FPGA experts tell me what is the easiest and least expensive way of getting started ? What eventually I want to implement (what I'm dreaming) are; * Communicate with four RS232 devices (115200baud) simultaneously * Control 16 parallel I/O lines * Encode/decode multi channel Radio Control signals ...


implementing ethernet server on FPGA or other choices

Started by Anonymous in comp.arch.embedded12 years ago 5 replies

i have to build a weather station. the data from the sensors is to be transmitted via ethernet and IP protocols.. i couldnt really reach a...

i have to build a weather station. the data from the sensors is to be transmitted via ethernet and IP protocols.. i couldnt really reach a decision on which of these develpoment tools should i use.. or which one is better..? 1. FPGA 2. PIC18F + EN28J60+eeprom ( all from microchip) 3. microntroller with built in ethernet controller OPTION1: its a college project, so FPGA's are readily ...


Resetting FPGA without Watchdog timer.

Started by ratemonotonic in comp.arch.embedded12 years ago 1 reply

Hi all , I am devoloping software fro microblaze using XPS and I dont have enough resources for a watchdog timer. I want to reset the FPGA...

Hi all , I am devoloping software fro microblaze using XPS and I dont have enough resources for a watchdog timer. I want to reset the FPGA after n number of error conditions have occured in software. Whats the most reliable way to reboot the Xilinx Spartan 3 FPGA? Any help will e much appreciated. BR Rate


DS80C400 and memory space with the SDCC compiler

Started by Fred in comp.arch.embedded15 years ago 7 replies

I am using a version of the TINIm400 and the TINIs400 reference design with an FPGA connected to CE3 and CE4. I wish to access the registers I...

I am using a version of the TINIm400 and the TINIs400 reference design with an FPGA connected to CE3 and CE4. I wish to access the registers I have placed in the FPGA but am wondering how to do it. I assume by default the FPGA is effectively at 0x60 0000 (for CE3) but how do I place a variable at this address so I can access with a C instruction. Apologies if it's very obvious.


MLC ECC with limited resources (FPGA/MCU)

Started by Vincent vB in comp.arch.embedded4 years ago 4 replies

Hi everyone, Now, I'm quite new in this, so please forgive me if I say silly things. I'm seeing whether or not it is possible (feasible) to...

Hi everyone, Now, I'm quite new in this, so please forgive me if I say silly things. I'm seeing whether or not it is possible (feasible) to implement MLC NAND error correction coding on our current system. We have a cortex-M3 (1MB Flash, 128K RAM) and a small FPGA with no DSP. On the FPGA I only have ~1K LUTs remaining. After searching the internet I found that BCH most commonly men...


more microblaze firmware blues. tool chain version problem?

Started by Anonymous in comp.arch.embedded12 years ago 1 reply

Hi all, I am currently working on porting some code on microblaze from a spartan 3 FPGA to a virtex 2 pro FPGA for expansion reasons. The...

Hi all, I am currently working on porting some code on microblaze from a spartan 3 FPGA to a virtex 2 pro FPGA for expansion reasons. The code which really works on a spartan 3 FPGA, just somehow does not seem to work on the virtex 2 pro. Here are some details: 1) for the spartan 3 FPGA, I used both EDK9.1i+ISE 7.1i and EDK9.2i +ISE9.2i the same firmware running on the spartan wor...


fpga and the particular case of xilinx

Started by sam in comp.arch.embedded10 years ago 2 replies

hiya in the particular case of fpga and the collaboration with xilinx remote monitoring, we could try to integrate the flow control of the...

hiya in the particular case of fpga and the collaboration with xilinx remote monitoring, we could try to integrate the flow control of the xilinx using centers of excellence. as a drawback i think that we could develop the recovery of the xilinx accurately. as a result when troubleshooting fpga and the concept of xilinx authorization, it might be better to increase the footprint of the ...


DDR SDRAM

Started by Anonymous in comp.arch.embedded13 years ago 2 replies

Hi all, I'm designing an FPGA based board. I needed to add DDR-SDRAM. Is there a way to interface the SDRAM to the FPGA other than develop/buy...

Hi all, I'm designing an FPGA based board. I needed to add DDR-SDRAM. Is there a way to interface the SDRAM to the FPGA other than develop/buy a controller to put inside the FPGA? I mean: are there external DDR-SDRAM controllers? Cheers


audio fingerprinting using fpga

Started by vibz86 in comp.arch.embedded10 years ago

Hi, I have to implement audio fingerprinting in fpga using verilog. As Im new to fpga, Im finding it hard to start with this. Can someone send me...

Hi, I have to implement audio fingerprinting in fpga using verilog. As Im new to fpga, Im finding it hard to start with this. Can someone send me any sample codes of audio fingerprinting or any usefull links that will help me to learn and do this project quickly --------------------------------------- This message was sent using the comp.arch.embedded web interface on http://www.E...


Cypress FX2 uc + Xilinx FPGA +windows system

Started by welber in comp.arch.embedded12 years ago 1 reply

Hi, I am new in FPGA and FX2 UC. I am looking for a good development board including xilinx FPGA and cyress Fx2 uc. I want to learn how to...

Hi, I am new in FPGA and FX2 UC. I am looking for a good development board including xilinx FPGA and cyress Fx2 uc. I want to learn how to program FPGA and FX2 uc. I went to several websites( usbp, Gnuradio, opal kelly, digilent...). They provide good development boards, but not all source codes open and no good tutorial written. Is any one know a good tutorial for Cypress FX2 uc + Xilinx F...


Hardware to test (FPGA-based) prototype?

Started by Alex Rast in comp.arch.embedded16 years ago 7 replies

I have an FPGA-based prototype for a PCI product in development. Since the intended product application will involve very high speed data...

I have an FPGA-based prototype for a PCI product in development. Since the intended product application will involve very high speed data transfers, we have designed all the I/O and internal busses in the FPGA to work on synchronous protocols. Now, however, I'm running into a real stumbling block. The problem is in testing the board. What I need to do is to be able to generate some te...


Purchasing memory DIMMs for embedded projects

Started by Theo Markettos in comp.arch.embedded7 years ago 13 replies

We're doing a project that uses about 150 DDR2 SODIMMs. Because we're using an FPGA, rather than a conventional motherboard chipset, the...

We're doing a project that uses about 150 DDR2 SODIMMs. Because we're using an FPGA, rather than a conventional motherboard chipset, the DDR2 controller IP demands we have to burn the DIMM timing into the FPGA when synthesising it, rather than reading the EEPROM at runtime. The FPGA DDR2 memory system is a lot less bulletproof than the average motherboard, so it needs to be heavily tested w...


Hardware (FPGA) Software(MCU) Interface

Started by ratemonotonic in comp.arch.embedded12 years ago 1 reply

Hi all , Can any one tell me a generic pattern to designing an interface between MCU(Configuring the Hardware ) and FPGA(used as...

Hi all , Can any one tell me a generic pattern to designing an interface between MCU(Configuring the Hardware ) and FPGA(used as an accelerator). My initial thoughts are to have a dual port RAM implemented in FPGA and accessed as a memory mapped device from the MCU and used to configure the Hardware. Is this viable ? is this the norm? Are there any tutorials on the net that can help(...


Recommended FPGA Families & Tools?

Started by Chris Graham in comp.arch.embedded15 years ago 10 replies

I'm just getting into FPGA design. What are good FPGA vendors in terms of good chips, good tools and good support? Also, if you've used the...

I'm just getting into FPGA design. What are good FPGA vendors in terms of good chips, good tools and good support? Also, if you've used the Cypress PSoC mixed analog & digital chips & tools, how did you find them? - Chris


74ls373 or 74ls374 to FPGA?

Started by Anonymous in comp.arch.embedded16 years ago 5 replies

Hi guys, I am developing a project that involves tens of 8 bit buffers. I am designing it with regular TTL logic but maybe in the future I...

Hi guys, I am developing a project that involves tens of 8 bit buffers. I am designing it with regular TTL logic but maybe in the future I will use FPGA if the project works. Well, I know developing with FPGA is better but I just don't have the initial investment and I have a lot of experience with TTLs. I can design it either with 74ls373 or 74ls374. If I use 74ls374, they will not sh...


FPGA configration Data/Firmware

Started by Anonymous in comp.arch.embedded15 years ago 1 reply

Hi all I have no idea regarding low level hardware. I should firgure out something about ALTERA ACEX. Question is like following. 1.Are...

Hi all I have no idea regarding low level hardware. I should firgure out something about ALTERA ACEX. Question is like following. 1.Are the FPGA configuration data and the firmware different? 2.How can I extract FPGA configuration data from ALTERA ACEX to my PC? 3.How can I extract firmware in EEPROM to my PC? P.S What I want to do finally is extrating data from FPGA and EEPROM and ...