I want to do Ethernet interface using FPGA DE0 Board

Started by dima shawahneh in comp.arch.embedded10 years ago

hello every one I was searching for the ability to design Ethernet interface with TCP/IP stack using Altera FPGA board DE0 ,and I really want to...

hello every one I was searching for the ability to design Ethernet interface with TCP/IP stack using Altera FPGA board DE0 ,and I really want to know if this is possible and what additional hardware is required,and how to do it This is a hardware senior project and im dealing with FPGA for the first time Thanks in advance --------------------------------------- Posted thro...


Pattern matching in FPGA

Started by vani.pratheeka in comp.arch.embedded11 years ago 3 replies

Hello everyone.... In my thesis work,i'm planning to implement a pattern matching circuit in an FPGA. But how to implement the corresponding...

Hello everyone.... In my thesis work,i'm planning to implement a pattern matching circuit in an FPGA. But how to implement the corresponding ASCII code of the pattern into an FPGA? Please help...


FPGA based processor vs. "hard" processor

Started by fp in comp.arch.embedded14 years ago 7 replies

I just finish reading the interesting thread of PIC vs AVR. I am not in the embedded area but have a related question. In recent...

I just finish reading the interesting thread of PIC vs AVR. I am not in the embedded area but have a related question. In recent Xilinx marketing stuff for Spartan-3 FPGA, it indicates that the 100K-gate FPGA now reaches $2 a piece, and the costs of softcore 8-bit processor (PicoBlaze) and 32-bit processor (MicroBlaze) are reduced to $0.10 and $0.48. Despite of the marketing hype, do you...


FPGA power optimize! Help!!!

Started by fpga_beginner in comp.arch.embedded12 years ago 3 replies

Hi all I have designed some FPGA based applications but very simple ones. Now I want to find some methods/algorithms in FPGA design to optimize...

Hi all I have designed some FPGA based applications but very simple ones. Now I want to find some methods/algorithms in FPGA design to optimize power. I search many documents (IEEE,..) but they are not in detail. I need some free documents and open source (or only detail steps) to implement power optimize algorthm. So i hope somebody can help me with useful links! Thanks


ethernet - DP83847 PROBLEM

Started by ashwin in comp.arch.embedded14 years ago 2 replies

Hello Everyone, I have few questions regarding the DP83847 PHY. I have this PHY on xilinx virtex fpga board. I need to write an ethernet mac...

Hello Everyone, I have few questions regarding the DP83847 PHY. I have this PHY on xilinx virtex fpga board. I need to write an ethernet mac in the fpga to send the packets to the PC through the PHY. Initially, to start with i am implementing the transmit module. 1) when i hardware reset the PHY, the link estabilishes between the PC and the fpga board, but whatever data i put on the MII ...


VGA and PAL output from FPGA

Started by Mark McDougall in comp.arch.embedded14 years ago 9 replies

I'm after a bit of advice on selecting some parts for a 'hobbyist' project which may eventually turn into a commercial product... I'm...

I'm after a bit of advice on selecting some parts for a 'hobbyist' project which may eventually turn into a commercial product... I'm developing a board with an FPGA which will produce RGB digital output ultimately for display on RGB (15kHz), VGA and PAL/NTSC composite video. Not necessarily simultaneously - worst case is a different FPGA image for the former two options. I've some e...


E1 stream and spartan 3E

Started by salimbaba in comp.arch.embedded10 years ago 1 reply

Hey, i want to terminate my E1 line into the spartan 3E fpga board. Can someone tell me how will i do that. I am terminating E1 line into...

Hey, i want to terminate my E1 line into the spartan 3E fpga board. Can someone tell me how will i do that. I am terminating E1 line into SN75183 line driver which is giving me a differential output signal. Now i want to terminate this signal into FPGA board, how will i do that? and if you have any other way to interface E1 and FPGA kit, kindly tell that too. Thanks Hassan --...


Cyconsole && Visual Studio ? ? Endpt xfers. CyAPI

Started by delbotero in comp.arch.embedded12 years ago 1 reply

Hello Everybody I am using cy7c68013 and my OS is Windows XP. I do not have Visual Studio 6, so I can not use CyAPI Library. I have...

Hello Everybody I am using cy7c68013 and my OS is Windows XP. I do not have Visual Studio 6, so I can not use CyAPI Library. I have connected the FX2 with an FPGA, the FPGA writes data to the FX2. FX2 is in Slave Fifo Mode. The signals EMPTY, FULL and PF are working right. I saw them with a Digital analizer. I want to see the data transferred from the FPGA in the computer. I have...


Doubts about PCI bus mastering

Started by Sink0 in comp.arch.embedded9 years ago 2 replies

Hi, i am implementing a PCI card using a FPGA. I am performing my tests on an old Pentium III computer that is basically fully based on the PCI...

Hi, i am implementing a PCI card using a FPGA. I am performing my tests on an old Pentium III computer that is basically fully based on the PCI bus. The OS is Linux. It is all working fine incluiding mastering but something weird happened today. I made a mistake at my FPGA code and at some point the FPGA started to burst write to to the computer and never stoped. I was controlling the compute...


FPGA/Embedded courses online or near Toronto

Started by zalzon in comp.arch.embedded15 years ago 3 replies

Hi, are there any fpga/embedded/pcb design courses online or in toronto that i as a newbie could take as a newbie. I'm new to the field of...

Hi, are there any fpga/embedded/pcb design courses online or in toronto that i as a newbie could take as a newbie. I'm new to the field of fpga and I have got a xilinx starter kit with the spartan III chip. I'd prefer to go through a full fledged instructor led course where i learn hardware design. Does anything like that exists? Thank you in advance for your advice.


USB 3.0 implementation on FPGA

Started by Maurice Branson in comp.arch.embedded10 years ago 12 replies

Hi everyone, I'm just about to start an implementation of a USB 3.0 interface in VHDL for data transfer from FPGA to a PC and vice versa....

Hi everyone, I'm just about to start an implementation of a USB 3.0 interface in VHDL for data transfer from FPGA to a PC and vice versa. The core should acts as a USB device for the PC. The core is intended for an FPGA projects where an "easy" interface to a PC is needed. Higher data rates as defined by the 3.0 standard should be possible with the implementation. Questions are...


For those starting with Cypress Ez USB FX2LP and FPGA interfaces -- PART 1

Started by makhan in comp.arch.embedded13 years ago

Hello, In order to start working with USB 2.0 data transfers, I used two boards for implementation and cross verification. The boards...

Hello, In order to start working with USB 2.0 data transfers, I used two boards for implementation and cross verification. The boards are: 1. Cy 3618 development board for FX2LP chips which support USB 2.0 transfers 2. FPGA developement kit which houses Cy7C68013A chip with all the connections to the FPGA. (By all connections I mean the ones which matter, as we will see later in the pos...


Using Ethernet to control/initialize FPGA based embedded system

Started by James Ma in comp.arch.embedded14 years ago 2 replies

Add a 100Mb/s or 1 Gb/s Ethernet MAC to your FPGA to enable control or transfer data from a PC. Simple & easy. No driver...

Add a 100Mb/s or 1 Gb/s Ethernet MAC to your FPGA to enable control or transfer data from a PC. Simple & easy. No driver programming. Direct control of FPGA state machines, registers & memories. No TCP/IP/UDP needed. Support multiple audio & video streams. Low gate count & low cost, no royalties. www.chipethernet.com


Postdoc / Summer Internship Opportunity on FPGA-Based Numerical Algorithm Design

Started by Anonymous in comp.arch.embedded14 years ago

Accelogic is seeking a talented research intern or Postdoc with FPGA experience, to assist with FPGA implementation aspects of a...

Accelogic is seeking a talented research intern or Postdoc with FPGA experience, to assist with FPGA implementation aspects of a new revolutionary family of hardware-oriented algorithms in the field of computational mechanics. This person will be part of the team in charge of algorithm/architecture design, and will contribute to the implementation of the world's first prototype of a hardware-...


ANNC: FPGA Design Software Webcast

Started by bart in comp.arch.embedded12 years ago 24 replies

Lattice is holding a webcast today, Wednesday, May 7th, on our latest version of our FPGA software design tools "ispLEVER 7.1 FPGA Design Tool...

Lattice is holding a webcast today, Wednesday, May 7th, on our latest version of our FPGA software design tools "ispLEVER 7.1 FPGA Design Tool Technical Rollout." The presenter will be Troy Scott, from our software marketing group. If you're interested, the event takes place live at 11am Pacific, 18:00 GMT. In addition, you will be able to view this webcast archive on-demand, at your conve...


How to synchronize a streaming system with FPGA+FT2232H FIFO

Started by dlopez in comp.arch.embedded10 years ago 19 replies

Hi, I'm having trouble figuring out how to architect a robust system using the FTDI chips in FIFO mode. I'm pretty sure some of you have been...

Hi, I'm having trouble figuring out how to architect a robust system using the FTDI chips in FIFO mode. I'm pretty sure some of you have been through this before. I'm using the FT2232H in synchronous FIFO, but my concerns are general. The system has PC FT2232H FPGA, and is used to both stream/receive data between the PC and the FPGA. I'm wanting to stream continuous data at about


Can XP embedded re-enumerate the PCI bus when a system has booted?

Started by Nial Stewart in comp.arch.embedded10 years ago 10 replies

I'm about to design a PC104+ board for a client with a largish FPGA on it, this will be driven by an SBC running XP embedded. A couple of...

I'm about to design a PC104+ board for a client with a largish FPGA on it, this will be driven by an SBC running XP embedded. A couple of factors mean there could be a delay of ~1 second until the FPGA has fully configured and I'm worried the SBC could have enumerated the PCI bus before the FPGA is ready to respond. I know in Linux you can force the system to re-enumerate the bus fairly ...


No way to program a Spartan 3 FPGA with a1,8V Digilent cable?

Started by blisca in comp.arch.embedded12 years ago 2 replies

I have a t home some "accurately scraped " FPGA Xilinx XC3S1500,having a VCCINT of 1,2 V, no way to use a cable rated 1,8 to 15 V to configure...

I have a t home some "accurately scraped " FPGA Xilinx XC3S1500,having a VCCINT of 1,2 V, no way to use a cable rated 1,8 to 15 V to configure it? Thanks, Diego,Italy


SPI with master at each end

Started by Anonymous in comp.arch.embedded5 years ago 2 replies

My target platform is an ARM-7 with an SPI connection to an FPGA. I need either device to be able to initiate data transfer, the approach I'm...

My target platform is an ARM-7 with an SPI connection to an FPGA. I need either device to be able to initiate data transfer, the approach I'm considering is to use a single additional data line from the FPGA to the ARM, "FPGA data waiting". When the ARM is notified of data waiting to be pulled back, it will initiate a rotation. If there happens to be data ready to go both ways, then the singl...


FT2232H synchronuous FIFO mode problem.

Started by Anonymous in comp.arch.embedded6 years ago

Hello, I have a custom PCB with FT2232H and FPGA on board. Writing from PC to FPGA via FT2232H in FT245 synchronuous FIFO mode workd perfect....

Hello, I have a custom PCB with FT2232H and FPGA on board. Writing from PC to FPGA via FT2232H in FT245 synchronuous FIFO mode workd perfect. However, I've got some problems with reading from FPGA to PC in this mode. Below is a part of my VHDL code responsible for it: USB_CLK: in std_logic; RST : in std_logic; TXE_n : in std_logic; WR_n : out std_logic; USB_DATA: inout std