Hi everyone, in the system I am using there is an ADSP21020 connected to an FPGA which is receiving data from a serial port. The FPGA receives...

Hi everyone, in the system I am using there is an ADSP21020 connected to an FPGA which is receiving data from a serial port. The FPGA receives the serial bytes and sets an interrupt and a bit in a status register once the byte is ready in the output register (one 'start bit' and one 'stop bit'). The DSP can look at the registers simply reading from a mapped port and we can choose either po...

hi..I'm a university student familiar with the only the basics of VHDL and FPGA implementation..For my project, I'm trying a make a sine wave,...

hi..I'm a university student familiar with the only the basics of VHDL and FPGA implementation..For my project, I'm trying a make a sine wave, ramp, triangular and square wave generator which outputs required wave of required amplitude and required frequency The FPGA is connected with DAC thru I2C bus.. The development board (nanoboard) has on- board freq of 20 mhz...now the dac being co...

Hello all, I'm pleased to announce the release of Avalda FPGA Developer v1.0 beta! It enables one to compile regular F# to RTL with...

Hello all, I'm pleased to announce the release of Avalda FPGA Developer v1.0 beta! It enables one to compile regular F# to RTL with parallel programming semantics. Our aim is to help make FPGAs available to a wider group of software programmers who may not have as much experience with HDLs or FPGAs. Please visit Avalda's site to download the beta and check out the blog! cheers, Ste...

I know others here have to deal with long life time support of designs, and I have one where I ahev to also supply the tools (free or paid) so...

I know others here have to deal with long life time support of designs, and I have one where I ahev to also supply the tools (free or paid) so that customer can support in at least 10 years time. The trouble is the design necessitates a PLD/CPLD/FPGA, so the requirements get quite onerous.... Device 100 registers min 50 I/O min Surface mount as TQFP/PQFP/PLCC ...

Hi all, I am using the Cypress FX2 to interface an FPGA to a PC via an USB2.0 link. The FX2 was configured to provide 4 bulk endpoints (+...

Hi all, I am using the Cypress FX2 to interface an FPGA to a PC via an USB2.0 link. The FX2 was configured to provide 4 bulk endpoints (+ synchronous FIFOs). Each bulk EP (2,4,6,8) is 512 byte long and is double buffered. All seems to work quite fine, but when a FIFO get full (i.e. the PC send more than 512 bytes) the EP does not take data any more, even if the FPGA empty the FIFO! The end...

Hi, I am currently working on a project where I have to transmit data from a PC to an FPGA board via Ethernet. For that purpose I use the...

Hi, I am currently working on a project where I have to transmit data from a PC to an FPGA board via Ethernet. For that purpose I use the HTG-V4PCIe evaluation board, which is a Xilinx Virtex-4 PCI Express Development Board from HighTech Global (http://www.hitechglobal.com/boards/v4pcie.htm). It features the Marvell Alaska 88E1111 Gigabit-Ethernet PHY which I use in combination with t...

Hi, I need an information. I need to have an FPGA Board and recive from a adc working between 20MHz and 100MHz, but i don't have any idea...

Hi, I need an information. I need to have an FPGA Board and recive from a adc working between 20MHz and 100MHz, but i don't have any idea who to do it because i don't know any site that sells this too things together! Thanks for the attention

I posted here before and got excellent responses, could you knowledgeable people also answer a simple questuion below? If you reply by email,...

I posted here before and got excellent responses, could you knowledgeable people also answer a simple questuion below? If you reply by email, REMOVE "SPAMNOMORE" in capital letters repeated in my address twice (edit address manually)!! We need to make sure Xilinx VirtexProII FPGA boards have a PCMCIA interface (hardware) and software support, and whether inteface is a regular one u...

The task is to boot the Cyclone FPGA from CPU. The standard way for doing that is Jam Bytecode Player available from Altera. It is workable,...

The task is to boot the Cyclone FPGA from CPU. The standard way for doing that is Jam Bytecode Player available from Altera. It is workable, however for the good variety of reasons, this JBC player is PITA. It seems possible to take the player output as a bit stream, pack it into a binary image and boot the FPGA by bit-banging from this image. The idea looks pretty obvious, and not ...

The Hydra chess computer looks like it is going to be the new world computer chess champion, and it is getting close to being the best chess...

The Hydra chess computer looks like it is going to be the new world computer chess champion, and it is getting close to being the best chess player, human or computer. What does this have to do with embedded systems? Hydra is FPGA-based, not PC-based - carrying on the tradition of Deep Blue and swinging the pendulum back to hardware. From what I have been able to gather, The Hydra che...

Should have crossposted with with comp.arch.fpga. ---------------------------------------------------------------- At the end of November we...

Should have crossposted with with comp.arch.fpga. ---------------------------------------------------------------- At the end of November we released the HSMC GPIB, this provides much needed functionality to any Altera dev kit with an HSMC connector including.... 8 * 10 bit ADC Inputs 8 * 10 bit DAC Outputs 2 * General Purpose 8 bit Digital IO ports 3 * RS232 Interfaces 2 * RS484 Inte...

Hi All, I have a FPGA system which requres better than 1pSec jitter. When I ask the Xtal MFG they advise there are 2 methods of measuring...

Hi All, I have a FPGA system which requres better than 1pSec jitter. When I ask the Xtal MFG they advise there are 2 methods of measuring Jitter Peak to Peak and an averaging method Measuring the same Xtal the result can be significatly differment values between the 2 methods. Does any one have any information on the 2 methods (or more) how to measure jitter. What would FPGA i...

I hope to get your feedback of what you think of integrating IAR EWARM (probably the same for EWAVR) with the hardware development scene. All...

I hope to get your feedback of what you think of integrating IAR EWARM (probably the same for EWAVR) with the hardware development scene. All our hardware design tools have Tcl scripting support for batching. I think it would be great to have the IAR simulator communicate with our FPGA simulator ( in our case ModelSim ) . This way we can make nightly builds possible and make tests with ...

Hello Friends, Seems like a cool forum... I think this is the best place to ask this questions. We design Thermal Imaging cameras which need...

Hello Friends, Seems like a cool forum... I think this is the best place to ask this questions. We design Thermal Imaging cameras which need quit a allot of custom image processing and custom sensor controls. What should we use FPGA or Micro controller? Camera and video/image processing Brief We have a 1024 by 768 12 bit per pixel(BW) image 30fp , coming in through a serial link. ...

Hi all, I've just written a report called "Single Top FPGA Tips". May be of interest for micro users who want to get started using...

Hi all, I've just written a report called "Single Top FPGA Tips". May be of interest for micro users who want to get started using FPGAs... http://www.burched.com/BurchED_Single_Top_Tips.pdf I tried to think of the best tip that I could give to a microntroller designer who has just started with FPGAs. That one is Single Top Tip #3. I hope that is useful! Kind regards, Anthony Burch ...

Hello, I am trying to use the OV7620 to get a RGB digital output using FPGA Spartan 2 (PEGASUS by Digilent)with the intention to display the...

Hello, I am trying to use the OV7620 to get a RGB digital output using FPGA Spartan 2 (PEGASUS by Digilent)with the intention to display the image on a regular monitor. The default output of the OV7620 is YCrCb, interlace scan, and 16-bit. While what I need is an RGB, progressive scan, and 8-bit output. I tried so hard to write into the OV7620 register to get the output I want but of no...

Hi, I have my motion control-system setup for a velocity loop. Encoder pulse periods are timed to calculate instaneous frequency and are...

Hi, I have my motion control-system setup for a velocity loop. Encoder pulse periods are timed to calculate instaneous frequency and are subtracted from a reference value to form an error signal. The timing and error generation occurs in an FPGA, the control-loop is implemented as a PID in a uC which samples the error register in the FPGA at 100 Hz. My issus is regarding noise: I hav...

======================================================== CALL FOR PAPERS ParaFPGA-2007 ...

======================================================== CALL FOR PAPERS ParaFPGA-2007 Parallel Computing with FPGA's A mini-symposium held in conjunction with the ParCo2007 conference "Parallel Computing" Juelich, Germany, September 4-7, 2007 URL: http://www.elis.ugent.be/parafpga e...

Hi, We are evaluating the interface to use for transferring data between an Altera/Xilinx FPGA and CPU. We are considering PCIe and GMII. This...

Hi, We are evaluating the interface to use for transferring data between an Altera/Xilinx FPGA and CPU. We are considering PCIe and GMII. This is going to be a point-to-point link with bi-directional data transfer hitting 500Mbps. The CPU we are using supports PCIe 1.1. My preference based on the research is to go for PCIe for the following reasons*. - High Throughput * PCIe 1.x at 2....

Hi, Is it feasible, or even possible to implement a complete router on a system on a chip (i.e. on one FPGA)? The FPGA would be one of...

Hi, Is it feasible, or even possible to implement a complete router on a system on a chip (i.e. on one FPGA)? The FPGA would be one of the higher-end FPGAs that exist. The router should be able to handle BGP and OSPF (i.e. traditional router functionality). For example, which of the following routers would be feasible/possible to implment on a system on a chip (the router should be ab...