We have developed data acquisition system which uses Cypress FX2 as the USB 2.0 interface. State machine for control and conversion of data...

We have developed data acquisition system which uses Cypress FX2 as the USB 2.0 interface. State machine for control and conversion of data between AD converters and FX2 is implemented using Xilinx Spartan 2 FPGA. The problem is that with higher data rates (up to 25 Mbit/s) we experience FX2 internal FIFO stalls and missing data on the receiving side. Small FIFO implemented inside FPGA d...

Hello, I?m looking for the best High Speed USB interface solution for my FPGA. My application is for the reception of Video Streaming through...

Hello, I?m looking for the best High Speed USB interface solution for my FPGA. My application is for the reception of Video Streaming through High Speed USB. ISP1582 (StEricson) points that : ?The internal generic Direct Memory Access (DMA) block allows easy integration into data streaming applications.? What?s the general behavior of the chip that eases the handling of streaming? What

I'm trying to implement an OV7620 sensor on a Spartan 3 (Xilinx FPGA) to display on VGA, the problem is to syncronize the sensor data with...

I'm trying to implement an OV7620 sensor on a Spartan 3 (Xilinx FPGA) to display on VGA, the problem is to syncronize the sensor data with VGA exit. The sensor is already programed to send data in progressive mode by 2 channels: channel Y G G G G channel UV B R B R Please, somebody can tell me how to syncronize with a monitor to display data on VGA? Regards!!!

Hi, I need to develop a embedded hardware (with a FPGA, example Xilinx(R) Spartan-3AN FPGA) capable of IDENTIFY what kind of USB web cam...

Hi, I need to develop a embedded hardware (with a FPGA, example Xilinx(R) Spartan-3AN FPGA) capable of IDENTIFY what kind of USB web cam is plugged-in (example webcam manufacturer, speed, data transfer rate, etc.), the USB will work with USB 1.0 or USB 1.1 (not USB 2.0) so a USB 2.0 web cam will work at USB 1.1. Due this is a embedded design, no computer interaction is required (this means that th...

Hi, I am currently working on a microblaze v6.00 core on FPGA and am developing an algorithm. This is what I am doing 1) matlab on PC...

Hi, I am currently working on a microblaze v6.00 core on FPGA and am developing an algorithm. This is what I am doing 1) matlab on PC sends data to microblaze (FPGA) via UART. RS232 hardware handshaking is deployed here. 2) the algorithm runs on microblaze to process the input data 3) microblaze sends the data back to matlab on PC. the setup I am working on works perfectly on a p...

Analog Devices, Altera and Danville Signal joined forces to create the ADDS-21261/Cyclone DSP & FPGA Evaluation Package featuring Danville's new...

Analog Devices, Altera and Danville Signal joined forces to create the ADDS-21261/Cyclone DSP & FPGA Evaluation Package featuring Danville's new dspstak 21261zx DSP Engine and dspstak c96k46 I/O Module. The dspstak 21261zx combines the power of a SHARC DSP and a Cyclone FPGA. With a supporting cast of SDRAM, Flash, EEProm, SPI, Programmable Clocks, USB and RS-232, the dspstak is great f...

I would like to automatically embed the Xilinx compile (synthesize) time into my FPGA. I have a script file that can put the time and date into...

I would like to automatically embed the Xilinx compile (synthesize) time into my FPGA. I have a script file that can put the time and date into my Verilog code. I would like to automatically call that script file from the Xilinx ISE everytime i run the synthesizer. Is there anyway for the ISE to call an outside routine (other than running the whole thing from a command line without the IS...

I am looking at a design which uses a PIC18F8520 whose USART is connected to a PC serial port running at a fairly high data rate. I am also...

I am looking at a design which uses a PIC18F8520 whose USART is connected to a PC serial port running at a fairly high data rate. I am also looking at the design of a serial port instantiated in an FPGA connected to the same data stream in an RS-485 network. Having to deal with the internal details of the FPGA "USART" makes me wonder about the internal details of the PIC USART. FOr instanc...

Hi, I have an fpga which is accessed from ARM as a memory-mapped device. A register in fpga is used to drive a I2C bus connected...

Hi, I have an fpga which is accessed from ARM as a memory-mapped device. A register in fpga is used to drive a I2C bus connected to a device . Two bits in the register represent clock and data lines of the bus. When I try to write into this register from ARM software as shown below, write is not happening. ARM is running at 48 Mhz. int* reg = 0x44400030; *reg = 0x3; T...

Hi, I'm working on high speed data transmission protocol aimed to receive data from low resource FPGA connected to the Ethernet PHY. The...

Hi, I'm working on high speed data transmission protocol aimed to receive data from low resource FPGA connected to the Ethernet PHY. The protocol is supposed to work on embedded Linux PC with high speed CPU and NIC. The protocol will be used only in a private network, and multiple FPGA systems will be connected via an Ethernet switch to single data collecting embedded system. All design...

I'm planning to build an ADC board with onboard buffer with DMA transfer from onboard buffer to computer's memory. Where can I find an ISA bus...

I'm planning to build an ADC board with onboard buffer with DMA transfer from onboard buffer to computer's memory. Where can I find an ISA bus board design example with DMA functionality using PLD or FPGA ? What would be the max paractical speed to transfer data from ISA bus to PC's memory?

Hi, I'd like to share with you my last development - a L3 protocol for transmission of data between low resources FPGA and an embedded...

Hi, I'd like to share with you my last development - a L3 protocol for transmission of data between low resources FPGA and an embedded system. It may allow you to use low cost/low resources FPGAs together with cheap Ethernet switches and simple Linux based embedded systems (or just reflashed Linux based Ethernet routers working as both a switch and an embedded system) to create data...

Hi Please,i would like to read something about controlling a soundcard with a microcontroller or FPGA,but i'm not able to find any link...

Hi Please,i would like to read something about controlling a soundcard with a microcontroller or FPGA,but i'm not able to find any link about,can you help me? thanks Diego

I'd like to interface a USB mouse to an FPGA. Does anyone have any advice regarding how best to go about doing this. I suspect the use of some...

I'd like to interface a USB mouse to an FPGA. Does anyone have any advice regarding how best to go about doing this. I suspect the use of some form of bridge chip or uC is the way to go but all these seem dominated by the assumption that a PC is involved. Has anyone had any experience in doing this kind of thing please? TIA, Rog.

Hello everybody. I'm interested in developing a JTAG system using a FPGA programmed in VHDL. Is there some good source on line that can help me...

Hello everybody. I'm interested in developing a JTAG system using a FPGA programmed in VHDL. Is there some good source on line that can help me in doing that? Where can I found the specification of JTAG standard? Are they free available?

Can anyone translate following for me. I found this as a default value into one of the slice blocks in system generator for xilinx FPGA....

Can anyone translate following for me. I found this as a default value into one of the slice blocks in system generator for xilinx FPGA. This block actually decode the address from the bus 32-ceil(log2(C_HIGH-C_BASE))

I am working on using a Z80 core on an fpga for use as an on chip serial terminal. I have not had much success in finding anything that I think...

I am working on using a Z80 core on an fpga for use as an on chip serial terminal. I have not had much success in finding anything that I think will fit. Something written in c and compilable with sdcc would be ideal. Anyone have any suggestions?

Hi Im trying to implement an 32bit Uart in cyclone 2 fpga(ep2c8t144). My requirements are as follows: speed: 9600bps In built fifo(depth 8)at...

Hi Im trying to implement an 32bit Uart in cyclone 2 fpga(ep2c8t144). My requirements are as follows: speed: 9600bps In built fifo(depth 8)at transmitter and receiver side. DMA and Modem controller not required. Can anyone help me with a vhdl code.

Hello, everybody I am a fun of FPGA, Embedded Systems, i have created a blog and i will post some articles, i am waiting for your comments and...

Hello, everybody I am a fun of FPGA, Embedded Systems, i have created a blog and i will post some articles, i am waiting for your comments and suggestions, Bye http://www.sammouda.blogspot.com/

Can someone give me a comprehensive list of the different file formats that are used with fpgas?

Can someone give me a comprehensive list of the different file formats that are used with fpgas?