Hi all, Is there some hardware RTL book like "Code Complete" by Steve McConnell? Thanks! Davy

Hi all, Is there some hardware RTL book like "Code Complete" by Steve McConnell? Thanks! Davy

Dear all, I am working on a hardware which has AT91SAM7S64, which works on 18.432 MHz main clock. This is the maximum frequency which can be...

Dear all, I am working on a hardware which has AT91SAM7S64, which works on 18.432 MHz main clock. This is the maximum frequency which can be seen on hardware. Now we are planning to buy an analog oscilloscope, we have seen several 30 MHz , 60 MHz and 100 MHz oscilloscopes. The 100 MHZ scope has the least rise time - 3.6 nS, for 60 MHz it is 5-6 nS, 30 MHz has around 11 nS. Can you suggest w...

Hello everybody, I'm new to embedded linux development. I want to write some routines that need 1uS timer resolution. I understand that the...

Hello everybody, I'm new to embedded linux development. I want to write some routines that need 1uS timer resolution. I understand that the ARM9 processors have 16 bit hardware timers. How do one use these timers in linux from 'C'. Anybody have any example code? If I was writing is Assembly, as I do with PICS, it would probably be easy.. but this is the first time working with ARM9 and Li...

In the thread above about RS485 driver enable, always originated by me, some new and interesting (for me) techniques has been descripted to use...

In the thread above about RS485 driver enable, always originated by me, some new and interesting (for me) techniques has been descripted to use a "wide" (32- or 64-bits) hardware up/down counter to read effectively without disabling interrupts, as I usually have done in the past. If the processor supports native hardware 32-bits counter, the problem doesn't exist: most probably it can b...

Hi all, i couldnt get what exactly "jazelle java hardware acceleration" mean? i found this in ARM processor manual. i couldnt find...

Hi all, i couldnt get what exactly "jazelle java hardware acceleration" mean? i found this in ARM processor manual. i couldnt find clearcut definition or explanation about this. can anyone put some light on this? thank you kaushik

Hi, I have used memory mapped I/O and understand it from a programmer's perspective, but I am curious as to how it gets implemented...

Hi, I have used memory mapped I/O and understand it from a programmer's perspective, but I am curious as to how it gets implemented in hardware. I basically want to know how physically(in hardware) this memory mapping takes place. For example, when the processor sends out 0xf000 on the address lines(bus) as part of a read request, how does the correct peripheral know that a read request...

I'm working with a custom designed hardware in fixed point arithmetic. I expect it won't be too difficult once I get my head wrapped around it,...

I'm working with a custom designed hardware in fixed point arithmetic. I expect it won't be too difficult once I get my head wrapped around it, but I seem to be spinning my wheels getting started. The arithmetic hardware has an 18x18 multiplier producing a 36 bit result feeding a three input, 55 bit adder. The other two inputs are a 54 bit input that is subtracted and a loopba

Hi First let me start by describing the hardware that I am using. I am using the SMSC LAN91C111 ethernet MAC & PHY which is driven by...

Hi First let me start by describing the hardware that I am using. I am using the SMSC LAN91C111 ethernet MAC & PHY which is driven by the Renesas 7144F processor (16-bit interface). I am not using a EEPROM in conjunction with the SMSC device hence the EEPEN pin is tied low and the IOS0-2 pins are left floating. Furthermore RBIAS is tied via a 11K resistor to ground. As the hardware stan...

The memory map has the read/write access for each hardware devices. If the hardware device only has read access, and we try to perform...

The memory map has the read/write access for each hardware devices. If the hardware device only has read access, and we try to perform write operation, that means the operation is denied. And I assume error will be generated, is that correct? please advice. thanks...

hello every one I was searching for the ability to design Ethernet interface with TCP/IP stack using Altera FPGA board DE0 ,and I really want to...

hello every one I was searching for the ability to design Ethernet interface with TCP/IP stack using Altera FPGA board DE0 ,and I really want to know if this is possible and what additional hardware is required,and how to do it This is a hardware senior project and im dealing with FPGA for the first time Thanks in advance --------------------------------------- Posted thro...

Hi all, I'm working on a hardware implementation (FPGA) of a lossless compression algorithm for a real-time application. The data will be fed...

Hi all, I'm working on a hardware implementation (FPGA) of a lossless compression algorithm for a real-time application. The data will be fed in to the system, will then be compressed on-the-fly and then transmitted further. The average compression ratio is 3:1, so I'm gonna use some FIFOs of a certain size and start reading data out of the FIFO after a fixed startup-time. The readou...

What is "hardware bring-up" in ur terms?

What is "hardware bring-up" in ur terms?

I'd like to implement a Power On Self Test to be sure all (or many) parts of the electronics are functioning well. The tests to be done to...

I'd like to implement a Power On Self Test to be sure all (or many) parts of the electronics are functioning well. The tests to be done to check external hardware depends on the actual hardware that is present. What about the MCU that features an internal Flash (where is the code) and RAM and some peripherals? Are there any strategies to test if the internal RAM or Flash are good? Do...

Hello All, I am implementing hardware handshaking with USART on AT91RM9200 board (24.6.3.12 in data sheet). I need to make RTS signal...

Hello All, I am implementing hardware handshaking with USART on AT91RM9200 board (24.6.3.12 in data sheet). I need to make RTS signal orignating from CP drop to allow the remote device with which the CPU is communicating t transmit information to the CPU. The data sheet states that the USAR needs requires the use of the PDC (peripheral DMA controller) fo reception when using hardware han...

I find that a lot of posts on this embedded group revolve around finding cheap or free tools to build embedded devices. However, in...

I find that a lot of posts on this embedded group revolve around finding cheap or free tools to build embedded devices. However, in my experience, I've found that productizing real embedded products is anything but cheap. It takes many thousands of dollars to build good hardware, program that hardware, and debug it. You need all sorts of gear from power supplies and logic analyzers to probes ...

I am wondering if the SoC (ARM/AMBA architecture) (where a whole system with upgradeable hardware modules/ IP cores can be stuffed inside a...

I am wondering if the SoC (ARM/AMBA architecture) (where a whole system with upgradeable hardware modules/ IP cores can be stuffed inside a single chip) will make all kinds of generalized microcontrollers (like PIC) obsolete. When PIC microcontrollers are used, they often need external hardware to help them, DSP blocks cannot be integrated into the chip at will (its all up to Microchip, w...

I'm designing a device that can display high resolution (at least 1080i or 1280x1024) images to a LCD monitor. I don't think that much...

I'm designing a device that can display high resolution (at least 1080i or 1280x1024) images to a LCD monitor. I don't think that much 2D/3D acceleration is needed for this purpose. Lower hardware cost is the first priority, although ease of development is important too. What is the best route? 1. Microprocessor only, to run embedded Linux and software-based display controller 2. Micr...

Hey everyone, I'm trying to get either Linux, NetBSD or some kind of Unix running on my Linksys BEFW11S4 embedded router. To do this, I need...

Hey everyone, I'm trying to get either Linux, NetBSD or some kind of Unix running on my Linksys BEFW11S4 embedded router. To do this, I need to know what kind of CPU and hardware they run. I've searched google to no avail. How do I figure out what kind of CPU and hardware it runs? Anyone know? - Farhan

This it is a message of Richard Staman creator of free softeare fundation and GNU on an idea to construct free hardware in FPGAs. ...

This it is a message of Richard Staman creator of free softeare fundation and GNU on an idea to construct free hardware in FPGAs. http://lists.duskglow.com/open-graphics/2007-January/008663.html http://en.wikipedia.org/wiki/Richard_Stallman Some nonfree architectures exist at the moment but it is known as a processor JAVA and Core of processor ARM work like in which I could run GNU/L...

Would that be possible? Or are USB floppy drives fixed to 1.44MB MS-DOS or MAC formats? The other way: Any compatibility of the USB floppies...

Would that be possible? Or are USB floppy drives fixed to 1.44MB MS-DOS or MAC formats? The other way: Any compatibility of the USB floppies to some sort of a upd765 or 37C65 floppy controller? Have to read old, CP/M formatted 3.5" floppies with actual hardware... Have to write software, of course, but will hardware allow to be initialized for some of the proprietary CP/M floppy formats...