PIC/AVR PWM + RS232 simultaneously?

Started by Anonymous in comp.arch.embedded11 years ago 6 replies

Are there any sub 10 USD AVR or PIC uC that can do hardware PWM at the same time as hardware RS232 ..? The source of my question is that I...

Are there any sub 10 USD AVR or PIC uC that can do hardware PWM at the same time as hardware RS232 ..? The source of my question is that I suspect that same timer is used both for bitrate generation and for PWM frequency+duty cycle.


booting the Linux on bare metal board.

Started by piyushpandey in comp.arch.embedded6 years ago 13 replies

Hi guys I was studying about the JTAG and than I all of sudden I got few questions in my mind regarding the linux booting on the embedded...

Hi guys I was studying about the JTAG and than I all of sudden I got few questions in my mind regarding the linux booting on the embedded hardware. Actually I know the procedure of how the linux boots on the hardware in embedded world and lots of stuff is available all over on the internet. But what I do not found is that how it begins, I mean the procedure is something like this: ...


Hardware book like "Code Complete"?

Started by Davy in comp.arch.embedded13 years ago 28 replies

Hi all, Is there some hardware RTL book like "Code Complete" by Steve McConnell? Thanks! Davy

Hi all, Is there some hardware RTL book like "Code Complete" by Steve McConnell? Thanks! Davy


Which oscilloscope to go for?

Started by faiyaz in comp.arch.embedded10 years ago 11 replies

Dear all, I am working on a hardware which has AT91SAM7S64, which works on 18.432 MHz main clock. This is the maximum frequency which can be...

Dear all, I am working on a hardware which has AT91SAM7S64, which works on 18.432 MHz main clock. This is the maximum frequency which can be seen on hardware. Now we are planning to buy an analog oscilloscope, we have seen several 30 MHz , 60 MHz and 100 MHz oscilloscopes. The 100 MHZ scope has the least rise time - 3.6 nS, for 60 MHz it is 5-6 nS, 30 MHz has around 11 nS. Can you suggest w...


Acess ARM9 hardware timers ( C and Linux )

Started by JimNorton in comp.arch.embedded10 years ago 6 replies

Hello everybody, I'm new to embedded linux development. I want to write some routines that need 1uS timer resolution. I understand that the...

Hello everybody, I'm new to embedded linux development. I want to write some routines that need 1uS timer resolution. I understand that the ARM9 processors have 16 bit hardware timers. How do one use these timers in linux from 'C'. Anybody have any example code? If I was writing is Assembly, as I do with PICS, it would probably be easy.. but this is the first time working with ARM9 and Li...


How to read a 32-bits hw counter on 8-bits microcontroller

Started by pozzugno in comp.arch.embedded5 years ago 8 replies

In the thread above about RS485 driver enable, always originated by me, some new and interesting (for me) techniques has been descripted to use...

In the thread above about RS485 driver enable, always originated by me, some new and interesting (for me) techniques has been descripted to use a "wide" (32- or 64-bits) hardware up/down counter to read effectively without disabling interrupts, as I usually have done in the past. If the processor supports native hardware 32-bits counter, the problem doesn't exist: most probably it can b...


what is "Jazelle Java hardware acceleration" -ARM

Started by coolblue in comp.arch.embedded14 years ago 5 replies

Hi all, i couldnt get what exactly "jazelle java hardware acceleration" mean? i found this in ARM processor manual. i couldnt find...

Hi all, i couldnt get what exactly "jazelle java hardware acceleration" mean? i found this in ARM processor manual. i couldnt find clearcut definition or explanation about this. can anyone put some light on this? thank you kaushik


Memory Mapped I/O Physical Implementation

Started by joshc in comp.arch.embedded14 years ago 7 replies

Hi, I have used memory mapped I/O and understand it from a programmer's perspective, but I am curious as to how it gets implemented...

Hi, I have used memory mapped I/O and understand it from a programmer's perspective, but I am curious as to how it gets implemented in hardware. I basically want to know how physically(in hardware) this memory mapping takes place. For example, when the processor sends out 0xf000 on the address lines(bus) as part of a read request, how does the correct peripheral know that a read request...


HELP! PIC18F8722 Port F Input Problem

Started by GaryI in comp.arch.embedded11 years ago

Hi, I'm using the 18f8722. What I've noticed is that when I power up the device and try to read Port F, I do not get anything back from...

Hi, I'm using the 18f8722. What I've noticed is that when I power up the device and try to read Port F, I do not get anything back from pin 7 until after a few seconds of waiting. The circuit is fine, and the port f pin 7 works fine on some hardware and this problem occurs on other. There's some kind of pic hardware issue with the functionality of using pins 5/6/7 on port f. I've do...


Lan91C111 PHY problem

Started by Ryan in comp.arch.embedded14 years ago 4 replies

Hi First let me start by describing the hardware that I am using. I am using the SMSC LAN91C111 ethernet MAC & PHY which is driven by...

Hi First let me start by describing the hardware that I am using. I am using the SMSC LAN91C111 ethernet MAC & PHY which is driven by the Renesas 7144F processor (16-bit interface). I am not using a EEPROM in conjunction with the SMSC device hence the EEPEN pin is tied low and the IOS0-2 pins are left floating. Furthermore RBIAS is tied via a 11K resistor to ground. As the hardware stan...


memory mapped I/O access question

Started by Ken in comp.arch.embedded13 years ago 3 replies

The memory map has the read/write access for each hardware devices. If the hardware device only has read access, and we try to perform...

The memory map has the read/write access for each hardware devices. If the hardware device only has read access, and we try to perform write operation, that means the operation is denied. And I assume error will be generated, is that correct? please advice. thanks...


I want to do Ethernet interface using FPGA DE0 Board

Started by dima shawahneh in comp.arch.embedded9 years ago

hello every one I was searching for the ability to design Ethernet interface with TCP/IP stack using Altera FPGA board DE0 ,and I really want to...

hello every one I was searching for the ability to design Ethernet interface with TCP/IP stack using Altera FPGA board DE0 ,and I really want to know if this is possible and what additional hardware is required,and how to do it This is a hardware senior project and im dealing with FPGA for the first time Thanks in advance --------------------------------------- Posted thro...


lossless compression in hardware: what to do in case of uncompressibility?

Started by Denkedran Joe in comp.arch.embedded12 years ago 25 replies

Hi all, I'm working on a hardware implementation (FPGA) of a lossless compression algorithm for a real-time application. The data will be fed...

Hi all, I'm working on a hardware implementation (FPGA) of a lossless compression algorithm for a real-time application. The data will be fed in to the system, will then be compressed on-the-fly and then transmitted further. The average compression ratio is 3:1, so I'm gonna use some FIFOs of a certain size and start reading data out of the FIFO after a fixed startup-time. The readou...


hardware bring up

Started by Anonymous in comp.arch.embedded14 years ago 5 replies

What is "hardware bring-up" in ur terms?

What is "hardware bring-up" in ur terms?


PDC w/ USART

Started by jgoshorn in comp.arch.embedded14 years ago 1 reply

Hello All, I am implementing hardware handshaking with USART on AT91RM9200 board (24.6.3.12 in data sheet). I need to make RTS signal...

Hello All, I am implementing hardware handshaking with USART on AT91RM9200 board (24.6.3.12 in data sheet). I need to make RTS signal orignating from CP drop to allow the remote device with which the CPU is communicating t transmit information to the CPU. The data sheet states that the USAR needs requires the use of the PDC (peripheral DMA controller) fo reception when using hardware han...


Is embedded on the cheap possible?

Started by speedplane in comp.arch.embedded12 years ago 10 replies

I find that a lot of posts on this embedded group revolve around finding cheap or free tools to build embedded devices. However, in...

I find that a lot of posts on this embedded group revolve around finding cheap or free tools to build embedded devices. However, in my experience, I've found that productizing real embedded products is anything but cheap. It takes many thousands of dollars to build good hardware, program that hardware, and debug it. You need all sorts of gear from power supplies and logic analyzers to probes ...


Will SoC completely replace generalized microcontrollers?

Started by Telenochek in comp.arch.embedded14 years ago 25 replies

I am wondering if the SoC (ARM/AMBA architecture) (where a whole system with upgradeable hardware modules/ IP cores can be stuffed inside a...

I am wondering if the SoC (ARM/AMBA architecture) (where a whole system with upgradeable hardware modules/ IP cores can be stuffed inside a single chip) will make all kinds of generalized microcontrollers (like PIC) obsolete. When PIC microcontrollers are used, they often need external hardware to help them, DSP blocks cannot be integrated into the chip at will (its all up to Microchip, w...


Software based or hardware based display controller?

Started by Fei in comp.arch.embedded11 years ago 2 replies

I'm designing a device that can display high resolution (at least 1080i or 1280x1024) images to a LCD monitor. I don't think that much...

I'm designing a device that can display high resolution (at least 1080i or 1280x1024) images to a LCD monitor. I don't think that much 2D/3D acceleration is needed for this purpose. Lower hardware cost is the first priority, although ease of development is important too. What is the best route? 1. Microprocessor only, to run embedded Linux and software-based display controller 2. Micr...


Linux or NetBSD on my Linksys BEFW11S4

Started by Anonymous in comp.arch.embedded13 years ago 3 replies

Hey everyone, I'm trying to get either Linux, NetBSD or some kind of Unix running on my Linksys BEFW11S4 embedded router. To do this, I need...

Hey everyone, I'm trying to get either Linux, NetBSD or some kind of Unix running on my Linksys BEFW11S4 embedded router. To do this, I need to know what kind of CPU and hardware they run. I've searched google to no avail. How do I figure out what kind of CPU and hardware it runs? Anyone know? - Farhan


XScale IXP425 network packet loss with Linux 2.4

Started by Daniel in comp.arch.embedded13 years ago

My IXP425 at 533 MHz running Linux 2.4 perfectly bridges 64-byte frames at 7 Mb/s (=10,000 frames/s), except that it loses a couple of...

My IXP425 at 533 MHz running Linux 2.4 perfectly bridges 64-byte frames at 7 Mb/s (=10,000 frames/s), except that it loses a couple of 100 frames every hour. Also, whenever I enter a command in the shell (Busybox), it drops some 200 frames instantly and reproducibly. The hardware frame buffer into which the MAC writes Ethernet frames is hardware-limited to 128 frames, so it would overrun in...