PIC18F252 Interrupts

Started by PigPOg in comp.arch.embedded12 years ago 2 replies

Can anyone shed some light on this problem please? It's likely to be something simple that I've overlooked. I'm using MPLAB 7.5 running on XP...

Can anyone shed some light on this problem please? It's likely to be something simple that I've overlooked. I'm using MPLAB 7.5 running on XP SP2. It's simple assembly code that services INT0 on the falling edge of port RC0 and services INT1 on the falling edge of RC2. Everything works OK except that should RC2 become active while INT0 is being serviced, as soon as the INT0 ISR completes...


Using Interrupts with WinAVR

Started by Mak in comp.arch.embedded14 years ago 8 replies

Hello all, This is an AVR specific problem. When I write a function for timer2 overflow as follows: // Timer 2 overflow interrupt service...

Hello all, This is an AVR specific problem. When I write a function for timer2 overflow as follows: // Timer 2 overflow interrupt service routine interrupt(SIG_OVERFLOW2)//SIG_INTERRUPT0)//SIG_OVERFLOW2) { // Place your code here PORTD ^= _BV(7); } and make with winavr, I get the following warnings: E:/AVR/WinAVR/testfiles/isr.c:6: warning: return type defaults to `int' E:/AVR/...


Need help in redirecting ISR after switching to a new execution image in MSP430

Started by an_anth in comp.arch.embedded4 years ago 2 replies

Hi, My earlier post was: Creating multiple images (Boot & App) in a project (IDE: CCS/IAR/CrossWorks) ? I am working...

Hi, My earlier post was: Creating multiple images (Boot & App) in a project (IDE: CCS/IAR/CrossWorks) ? I am working with: Microcontroller: MSP430F1611 IDE: CrossWorks for MSP430 Right now I have managed to create and load the 2 images, namely, Bootloader and Application, in separate memory locations. And I am able to jump to the Application code by using the address of its "main...


HC11 interrupt handling query

Started by bruce varley in comp.arch.embedded13 years ago 4 replies
ISR

Hi, I have an HC11 counting edges from an external, asynchronous source, into the pulse accumulator (PA in what follows). Pulse rate is 'slow'...

Hi, I have an HC11 counting edges from an external, asynchronous source, into the pulse accumulator (PA in what follows). Pulse rate is 'slow' in relation to processing and program loop cycle. The count may exceed 255, so I'm using a small ISR on pulse accumulator counter overflow to increment a high order counter byte. I need to count the pulses over a 1 second window, every second, as f...


PIC Input Capture

Started by DssSouth in comp.arch.embedded16 years ago 2 replies
ISR

Below is the ISR for CCP2(fall edge), the input is also tied to CPP1(rise). Only the CCP2 interrupt is enabled. I need to get Pulse Width and...

Below is the ISR for CCP2(fall edge), the input is also tied to CPP1(rise). Only the CCP2 interrupt is enabled. I need to get Pulse Width and Pulse Rate from this interupt, and I would use the following equations; PW = fall(n)-rise(n); PR = fall(n+1) - last_fall(n); PW works, but I can't get PR to work, fall always seems to be equal to last_fall, equating to zero. I would also like to r...


properly handling shared-interrupts in hardware and linux-driver

Started by markus schorer in comp.arch.embedded16 years ago 4 replies

hi all, i have an interrupt-related problem on a self-designed pc104-board: i have several int-sources connected to a register and an...

hi all, i have an interrupt-related problem on a self-designed pc104-board: i have several int-sources connected to a register and an edge-detector. if an edge is detected an int is raised. the shared isr's then check the register to see if they need to service their device. the int is cleared by writing to the register. my problem: sometimes no more ints are generated. reloading a dr...


Freescale 9S12X:I'm not able to route interrupt to XGATE

Started by blisca in comp.arch.embedded7 years ago

Hi,from Milan,Italy I want to use the XGATE coprocessor in a 9S12X Freescale uC I followed indications in AN3144 but i cant reach the...

Hi,from Milan,Italy I want to use the XGATE coprocessor in a 9S12X Freescale uC I followed indications in AN3144 but i cant reach the interrupt routine for XGATE in case oft PeriodicInterrupTimer0 interrupt,so i ask your help: The interrupt is correctly managed if routed to the main CPU If i try to route it to the XGATE i finish in : ISR(Cpu_Interrupt) { asm(BGND); } w...


How best to "detect a min pulse width" using C18 + 18F1330 pic

Started by Dennis in comp.arch.embedded9 years ago 15 replies

I'm still learning C, and am having some problems with the code to detect a pulse over a specific width. My method is: The pulse is...

I'm still learning C, and am having some problems with the code to detect a pulse over a specific width. My method is: The pulse is negative going, normal state is high: _____ ________ \_____/ Pulse duration time is measured by a register 'Break_Time' which is incremented in the ISR each time TIMER1 overflows. I'm using interrupt INT0 to sense the start and finis...


HC908GR4/8 SPI interrupt problem

Started by Fred in comp.arch.embedded15 years ago 5 replies

The HC908GR4 acts as a SPI slave, the baud rate of the host clock is only around 5K bps. When the host sends a packet of 8-bytes to the HC908GR4,...

The HC908GR4 acts as a SPI slave, the baud rate of the host clock is only around 5K bps. When the host sends a packet of 8-bytes to the HC908GR4, it only generate the first Rx interrupt and the ISR only read the first byte. Then no more interrupt occurs, even on the subsequence packets. It seems just reading from the Status and Control Register then reading from the Data Register does not c...


"SLEEP" Mode repetition

Started by Devyn in comp.arch.embedded15 years ago 4 replies

Hi All! I have a PIC16f877a. I want to work with the device mainly in sleep, wake on RB change, do some stuff (say led blink) and go back to...

Hi All! I have a PIC16f877a. I want to work with the device mainly in sleep, wake on RB change, do some stuff (say led blink) and go back to sleep. This code works fine if i put the blink code in the ISR. How do i use this code in the main program in C? I tried :- main() { // initialization of interrupts etc... s1 :asm("SLEEP"); asm("NOP"); RE0=0x1; delay(); a fn. for 1s delay ...


AVR Silly Interrupt problem

Started by ja.....@.mail.com in comp.arch.embedded14 years ago 17 replies

I have timer0 set to overflow and generate an interrupt, but for whatever reason AVR Studio doesnt seem to be doing what the ISR is supposed to...

I have timer0 set to overflow and generate an interrupt, but for whatever reason AVR Studio doesnt seem to be doing what the ISR is supposed to be doing! I'm attaching the code here, can you find something that I'm missing!? Is this a problem with the simulation in AVR Studio or with the code itself? I haven't tested it on a device yet. #include #include


gdb stub for AVR: breakpoints and single stepping

Started by Ico in comp.arch.embedded14 years ago 3 replies

Hello, I'm working on a `gdb stub' to allow debugging of code in an Atmel AVR processor using gdb running on the host platform. Communication...

Hello, I'm working on a `gdb stub' to allow debugging of code in an Atmel AVR processor using gdb running on the host platform. Communication between gdb and the stub is done over RS232. At this moment my platform is the at90can128, but other AVR types should work as well with little change. The stub is implemented as an interrupt handler on the serial-rx interrupt. When the ISR is acti...


Multiple Interrupt handling in XPS 8.2i

Started by moon in comp.arch.embedded10 years ago

Iam using XPS 8.2i.I have built a custom peripheral and attached it to MicroBlaze (v 5.0) via OPB bus.My peripheral generates the...

Iam using XPS 8.2i.I have built a custom peripheral and attached it to MicroBlaze (v 5.0) via OPB bus.My peripheral generates the two interrupts.These interrupts pins are input to the interrupt controller INTC (1.00 c). Initially both interrupts are disabled.Then only high priority interrupt is enabled. What my objective is that when a high priority interrupt occurs:in its ISR it should dis...


H8s/2144 interrupts

Started by Arthur Richards in comp.arch.embedded15 years ago 3 replies

I have two interrupt sources. ( serial comms & a timer overflow). What I would like to do is have the timer interrupt set at a higher priority...

I have two interrupt sources. ( serial comms & a timer overflow). What I would like to do is have the timer interrupt set at a higher priority so that it can interrupt the serial interrupt ISR. I have set the ICR timer bit hi and the SYSCR INTM0 bit hi but the comms is still holding off the timer. I see a reference to I & UI bits. What are they? Does anyone know how to do this. TIA ...


8051 problem with serial port and timer

Started by MP in comp.arch.embedded13 years ago 3 replies

Hi everybody, I am using a AT89C51ED2 in my design and I have a problem with its timer and UART simultanous function. Timer and serial port work...

Hi everybody, I am using a AT89C51ED2 in my design and I have a problem with its timer and UART simultanous function. Timer and serial port work fine seperatly but when they are gathered in one code, timer ISR stops functioning. here is sample of the code written in keil. #include /* special function register declarations */ #include /*


About Interrupt Problem in RHEL-5

Started by mahi in comp.arch.embedded9 years ago 1 reply

Hi All, I have developed one PCI driver, The Interrupts are working in 2.4 kernel (Redhat-9), and also it is working in RHEL-AS-4 (2.6 kernel),...

Hi All, I have developed one PCI driver, The Interrupts are working in 2.4 kernel (Redhat-9), and also it is working in RHEL-AS-4 (2.6 kernel), But It is not working in RHEl-5 using Interrupt mode. After Enabling the PCI Interrupt also, It should automatically enter into ISR, But it is not happening in RHEL-5 (2.6.18-53.el5)....what might be the problem. I have used request_irq(IRQLine...


Synchronizing user space threads with kernel space in linux

Started by Mad...@Spammers in comp.arch.embedded15 years ago 17 replies

I want to synchronize a user space thread to an external event that generates an interrupt. I thought of using the following approach: the ISR...

I want to synchronize a user space thread to an external event that generates an interrupt. I thought of using the following approach: the ISR that treats the interrupt does a quick processing (such as data capture and buffering) and then sends data to the user space thread through a message queue or signals to the thread waiting on a semaphore and it gets the buffered data from shared memory...


CrossWorks CTL and interrupt handling

Started by marks65 in comp.arch.embedded12 years ago 1 reply

I'm newish to Crossworks/CTL and need to confirm my understanding of the IRQ and FIQ stuff. So the question is... CTL redirects the IRQ...

I'm newish to Crossworks/CTL and need to confirm my understanding of the IRQ and FIQ stuff. So the question is... CTL redirects the IRQ handler to its own handler for ALL IRQ interrupts(correct?), where it calls the ISR in question and then CTL task handler stuff. If this is so, and I want to have a fast response to an EINT0 external interrupt then I have no choice but to accept the overhea...


Announcement: C-Code generator from UML state charts - new version 1.6.2

Started by Peter Mueller in comp.arch.embedded10 years ago 1 reply

Hello list readers, SinelaboreRT is a console application that generates C-code from UML state charts. The UML state charts can be designed...

Hello list readers, SinelaboreRT is a console application that generates C-code from UML state charts. The UML state charts can be designed with Cadifra UML editor, Enterprise Architect, UModel or Magic Draw. The generation process can be widely adjusted to your needs and produces code that can even run in an ISR. SinelaboreRT was built especially for embedded real-time/low power system...


Sleeping PICs Lie ? - WDT + GIE <> ISR but Just Resumes Main Code

Started by B1ackwater in comp.arch.embedded11 years ago 10 replies

OK ... a minor mystery ... While I've used PICs for many things, I've never made use of the SLEEP mode. For my 18f2620, the docs state...

OK ... a minor mystery ... While I've used PICs for many things, I've never made use of the SLEEP mode. For my 18f2620, the docs state : "All external interrupts (INT0, INT1 and INT2) can wake-up the processor from SLEEP, if bit INTxE was set prior to going into SLEEP. If the global interrupt enable bit GIE is set, the processor will branch to the interrupt vector following wake-up." ...