RTOS stack overflow

Started by brOS in comp.arch.embedded10 years ago 17 replies

Dear all, I am testing my own kernel for MSP430. I am measuring highest frequency for square signal that MSP430 with my kernel can repeat on...

Dear all, I am testing my own kernel for MSP430. I am measuring highest frequency for square signal that MSP430 with my kernel can repeat on its output. Square signal is connected to one of the interrupt pins, so on every high to low or low to high signal edge port interrupt is generated. In port ISR I am releasing semaphore on which my task is blocked. After task is unblocked its job is to ...


8259 Interrupt Controller OCW2 register

Started by HT-Lab in comp.arch.embedded12 years ago
ISR

Hi all, I am trying to figure out how an 8259 OCW2 register behaves, more specifically if the "Automatic Rotation" bits of OCW2 are latched...

Hi all, I am trying to figure out how an 8259 OCW2 register behaves, more specifically if the "Automatic Rotation" bits of OCW2 are latched or not. For example, if I want to automatically rotate interrupt priorities on a Non-Specific EOI, do I a) Issue a "Rotate on non-specific EOI command" to OCW2 during initialisation and then issue a Non-Specific EOI at the end of my ISR. or ...


UART receive issue

Started by mak in comp.arch.embedded11 years ago 4 replies

Hello, I am facing an issue in UART receive. When i enable the receive enable bit in the control register, framming and break error bit...

Hello, I am facing an issue in UART receive. When i enable the receive enable bit in the control register, framming and break error bit interrupt is raised. I clear the error bit in ISR. Then whatever i transmit by my PC (hyperterminal) its not received by UART on the board. Note: Transmit from board to PC is working fine. Please suggest a solution of this issue. Thank you! Regards, M...


Interrupt Control Register of Renesas M16C

Started by Steven Woody in comp.arch.embedded11 years ago 8 replies
ISR

Hi, In M16c, after a peripheral interrupt was disabled by setting it's interrupt control register's LVL bits to 0, and then the...

Hi, In M16c, after a peripheral interrupt was disabled by setting it's interrupt control register's LVL bits to 0, and then the interrupt just comes in, and after a while the interrupt was enabled by setting the LVL to a value other than 0. I want to ask, in this time, will the ISR be invoked? Put it this way: Will a peripheral interrupt keep pending while it is disabled? Thanks.