I've included a function below and the generated STM8 assembly-language. As it ends up (based on the assembly-language), the function is...

I've included a function below and the generated STM8 assembly-language. As it ends up (based on the assembly-language), the function is interrupt safe as intended. My question is, let's assume I have this: DI(); if (x) x--; EI(); where DI and EI just expand to the compiler's asm( ) feature to insert the right machine instruction to disable and enable interrupts, ... Is th...

In the thread above about RS485 driver enable, always originated by me, some new and interesting (for me) techniques has been descripted to use...

In the thread above about RS485 driver enable, always originated by me, some new and interesting (for me) techniques has been descripted to use a "wide" (32- or 64-bits) hardware up/down counter to read effectively without disabling interrupts, as I usually have done in the past. If the processor supports native hardware 32-bits counter, the problem doesn't exist: most probably it can b...

I was looking for low footprint RTOS (with minimal capability of Message Q, semaphore, memory mgmt, few tasks & interrupts) and found silRTOS...

I was looking for low footprint RTOS (with minimal capability of Message Q, semaphore, memory mgmt, few tasks & interrupts) and found silRTOS fits for my budget size(

Anybody know of a freeRTOS implementation for the Cirrus EP93xx chip? I am trying to keep the basic set of interrupt functions used in...

Anybody know of a freeRTOS implementation for the Cirrus EP93xx chip? I am trying to keep the basic set of interrupt functions used in the original ARM port used for other devices. This requires a direct vectored jump to a program memory location held in the VIC address register when an IRQ arives. In many ARMs this is simply done by including a "ldr pc,[PC,#-0xFF0]" in the IRQ entry of t...

I need a whinge. Bloody Zilog's so-called ez80 software has been running me ragged for over a week. The code executes perfectly on the...

I need a whinge. Bloody Zilog's so-called ez80 software has been running me ragged for over a week. The code executes perfectly on the development kit, crashes on the target. Running off with the fairies, Program counter pointing anywhere. MUST be a hardware fault. Spent ages writing evermore sophisticated tests to fault the RAM. No failures at all. OK, spurious interrupts- had every...

Hi, I'm very new to the motorolla chips (or programming MC for that matter). i am tryin to figure out how to write an interrupt...

Hi, I'm very new to the motorolla chips (or programming MC for that matter). i am tryin to figure out how to write an interrupt service routine for the Keyboard interrupt. > From a not so reliable sample code i have: interrupt 15 void KBI_ISR (void) { ...some code } is this right? if so, can i replace KBI_ISR with some other name? and if i want to write an interrupt for IRQ

Watching all this discussion about debugging with an LED and such, I was wondering if anyone else writes software UARTS for debug info. I've...

Watching all this discussion about debugging with an LED and such, I was wondering if anyone else writes software UARTS for debug info. I've written a 9600 baud tx-only UART for AVR's in 35 assembly instructions. The data out can be inverted so that you can connect the tx I/O pin directly to your terminal without an inverter or driver. Timing is by software timing loops so interrupts...

Hi, I am reading MPC8280 PowerQUICC=99 II Family Reference Manual. In section 4.3.1.1, it mentioned two words: grouped, spread. the sentence is...

Hi, I am reading MPC8280 PowerQUICC=99 II Family Reference Manual. In section 4.3.1.1, it mentioned two words: grouped, spread. the sentence is like this: The SIU interrupt configuration register (SICR), shown in Figure 4-10, defines the highest priority interrupt and whether interrupts are grouped or spread in the priority table, I have some trouble to understand this. what is grouped...

I'm looking for any good advice on working with the capture/compare unit of the eZ8. (eZ8 documentation references below) The goal is to...

I'm looking for any good advice on working with the capture/compare unit of the eZ8. (eZ8 documentation references below) The goal is to capture the time between two events (high signals). It must reliability capture these events continuesly with the highest possible precision. To complicate the matter, the times scale beyond the 16-bit counter. Multiple interrupts are generated and while...

Sorry if this is a bit of a clueless newbie question, but here goes. Running under Cygwin, with GDB and the embedded PowerPC simulator, PSIM. I...

Sorry if this is a bit of a clueless newbie question, but here goes. Running under Cygwin, with GDB and the embedded PowerPC simulator, PSIM. I can load the code OK, but when I try to run it, I get Type 7 ("Program") exceptions. This occurs even if interrupts are disabled by setting MSR=0. As I understand, Exception 7 originates from certain floating-point problems, which should not apply i...

hi all, I'm wondering what are the main parameters when talking about kernel performance...and when I say kernel I mean basic stuff, like...

hi all, I'm wondering what are the main parameters when talking about kernel performance...and when I say kernel I mean basic stuff, like context switching, blocking time, time for finding task of the highest priority etc... I am familiar with following parameters: -interrupt latency(which is, as I understand, directly proportional to length of sections of code where interrupts are disabled...

Just starting to use the TMS470R1B1, which is a high-temp, high-rel processor with the ARM M3 core. At the customer's insistence I'm using...

Just starting to use the TMS470R1B1, which is a high-temp, high-rel processor with the ARM M3 core. At the customer's insistence I'm using the IAR IDE, and interrupts are all f***ed up. Even the IAR demos don't work, and the register definitions in the ever-so-easy-to-find files don't match the documentation or, apparently, reality. I'm trying to figure out how much of this is me, h...

I have a problem with an atmega168. On my test board I have a jumper on PB1 and a LED on PD5, using internal 8MHz RC-clock. Given the...

I have a problem with an atmega168. On my test board I have a jumper on PB1 and a LED on PD5, using internal 8MHz RC-clock. Given the following program: #include #include #include INTERRUPT(SIG_PCINT0) { unsigned short i; char j; for(j=0; j

Hi Group, Intro I've been programming for a long time (to long to mention!), but 99% of my programming has been for 'desktop' PCs under DOS...

Hi Group, Intro I've been programming for a long time (to long to mention!), but 99% of my programming has been for 'desktop' PCs under DOS and UNIX using C. I've rarely had to worry about interrupts, watchdogs etc. Well now I have to! The target will be a Radio with an 8-bit NEC Micro controller (non-RTOS). My initial task is to Tx/Rx data over serial comms (again, I hope in C). The da...

I have a system that needs to spend the majority of its time in a sleep mode (using internal 30kHz oscillator), wake to respond to some...

I have a system that needs to spend the majority of its time in a sleep mode (using internal 30kHz oscillator), wake to respond to some interrupts (either still running at 30kHz or 6MHz external crystal) and occasionally perform some high speed tasks (using the 6MHz external with a PLL ---> 50MHz). I've neglected my power management to this point and now I am at the tail end of the project looking

Hi there! I am trying to get my interrupts working on my mc9s12ne64 board. The code is as...

Hi there! I am trying to get my interrupts working on my mc9s12ne64 board. The code is as follows. ####################################################\ninclude /* common defines and macros */ #include /* derivative information */ #pragma LINK_INFO DERIVATIVE "1" void main(void) { long i; int a,b; //init PLL so PLL is 50MHz and bus is 25 MHz

The manual from Motorola says... ************************ The code that prefetches must be in cache-inhibited memory as in the following...

The manual from Motorola says... ************************ The code that prefetches must be in cache-inhibited memory as in the following example: # Assuming interrupts are turned off, cache has been flushed, # the MMU is on, and we are executing in a cache-inhibited # location in memory # LR and r6 = Starting address of code to lock # CTR = Number of cache blocks to lock # r2 = nonzero nu...

hi, I'm using a custom designed board having LH79520 with 32MB micron SDRAM & 8MB flash. Very similar to LogicPD board, but without the extras...

hi, I'm using a custom designed board having LH79520 with 32MB micron SDRAM & 8MB flash. Very similar to LogicPD board, but without the extras (lan, audio, CPLD, buffers etc). It does have a external reset chip. The board works fine when no interrupts are used. However, when I try to use the timer interrupt, it works intermittently between power-ups. Meaning, the interrupt is working afte...

Hi, I am using the MPC5200B processor, the Lite5200B evaluation Board. I have a Rx BestComm Task for receivng data on PSC1 (Uart Mode) from...

Hi, I am using the MPC5200B processor, the Lite5200B evaluation Board. I have a Rx BestComm Task for receivng data on PSC1 (Uart Mode) from the Hyperterminal of the host desktop. For downloading the executable I am using the Windriver ICE, Vision Click. Compiler is diab. When I set up the Rx Task and start it and then send a text file through the Hyperterminal I get BestComm interrupts a...

File In Keil is linker configuration file (*.l51) .I can set fix adress to procedure:, function, constants or all .c files. Example: --- code...

File In Keil is linker configuration file (*.l51) .I can set fix adress to procedure:, function, constants or all .c files. Example: --- code (100h,?PR?MYPROCEDURE?TESTOFS(4000h)) --- My hardware require: some procedures must be in fix address code (such as interrupts). Is it posiible in SDCC ??? please help