Hey everyone What options do i have to interface external memory for my arm7 chip? CF, USB, PSD? Thanx :-) xarion

Hey everyone What options do i have to interface external memory for my arm7 chip? CF, USB, PSD? Thanx :-) xarion

I have in mind to store a lot of data acquired by an autonomous measurement board build around a MSP430, on a removable memory stick. If...

I have in mind to store a lot of data acquired by an autonomous measurement board build around a MSP430, on a removable memory stick. If possible in a "disk" format, readable on some laptop. Did somebody realize it? Do you know about an application note about that ? Thanks for any information and help p.

Hello group, I have been tasked with investigating possible solutions for a new product. I have normally used micros with flash/ram memory...

Hello group, I have been tasked with investigating possible solutions for a new product. I have normally used micros with flash/ram memory onboard, but now we need to have atleast 1MB codememory and the same amount of RAM, so I have been looking for a while to find some possible setup. It appears to me that singlechip MCU's are much more popular (naturally), but I would like to ask all of ...

Hi All, I am looking at a project which needs removable memory. This is going inside an industrial control system and will be moved...

Hi All, I am looking at a project which needs removable memory. This is going inside an industrial control system and will be moved in-frequently. Being an amateur photographer I though CF (Compact Flash) It is easily available up to 8GB at the moment and is physically easy to handle. Some one else suggested SD cards as they are smaller and as CF is "old" it might disappear soon. ...

Please help me understand various modes in which CF can be accessed. I understand that there are 3 access modes of CompactFlash card: 1. PC...

Please help me understand various modes in which CF can be accessed. I understand that there are 3 access modes of CompactFlash card: 1. PC Card ATA memory mode (uses OE-, WE-) 2. PC Card ATA IO mode (uses IORD-, IOWR-) 3. true IDE mode (complies to ATA-4) I have following doubts: 1. In PC Card ATA memory mode, how does the host access complete memory space when only 11 addre...

Hi NG! I have a problem to access the 256 bytes of special information memory (0x1000-0x10ff) of the MSP430F413 using the msp430-gcc...

Hi NG! I have a problem to access the 256 bytes of special information memory (0x1000-0x10ff) of the MSP430F413 using the msp430-gcc toolchain. I've tried the .org statement (.org 0x1000) but it seems to address relative to the given section (.text, .data ...). Is there a section name for the information memory, too? How can I handle this address range? Thanks for any information!

Hi, I have been able to run Michel Xhaard's spcaview (spcaClient) on VMware Linux pc but when I ran it on friendlyarm9 I get a segmentation...

Hi, I have been able to run Michel Xhaard's spcaview (spcaClient) on VMware Linux pc but when I ran it on friendlyarm9 I get a segmentation fault. I changed the memory on the Vmware to the memory but it still run well. After reading about segmentation fault error, I suspect the only function in spcaClient that access memory. The function is below: void resize (unsigned char *dst,unsigned cha...

Hello, All! What is the common practice for flash memory application for bootloader: NOR or NAND? And the same question - for kernel image...

Hello, All! What is the common practice for flash memory application for bootloader: NOR or NAND? And the same question - for kernel image storing and file system. Thanks in advance. With best regards, Roman Mashak. E-mail: mrv@tusur.ru

Hi all! About "code banking" using keil compiler, I read first 32k memory of bank is kept as common area and rest 32k for bank in each...

Hi all! About "code banking" using keil compiler, I read first 32k memory of bank is kept as common area and rest 32k for bank in each bank. Can we reduce common area memory and increase actual bank memory as per the requirement? Best regards, Ishita

Hi, Is there any Flash Memory that acts partly as RAM also ? Thx in advans, Karthik Balaguru

Hi, Is there any Flash Memory that acts partly as RAM also ? Thx in advans, Karthik Balaguru

Hi. I'm working on a TI OMAP processor. My questions are as follows: If I can work with an identity mapping between physical and...

Hi. I'm working on a TI OMAP processor. My questions are as follows: If I can work with an identity mapping between physical and virtual address spaces, is there a benefit to using the MMU at all? Isn't it better to leave it Disabled? Is there a downside to using the MMU? Does it cause extra memory reads from the Translation Table in memory? Thanks, s.

We are using M25P32 flash memory in one of the projects. It is used as a boot memory; normally, it is written only once or twice. However,...

We are using M25P32 flash memory in one of the projects. It is used as a boot memory; normally, it is written only once or twice. However, there is a significant percent of failures; almost 25% of parts quit working after several weeks of operation. The failure is gradual: it starts like occasional hangups while reading or programming, then it happens more and more often, and at last...

I've read the F manuals and I'm still no wiser... anyone know how I can get a memory usage listing from gcc (I'm using msp430-gcc)? I've tried...

I've read the F manuals and I'm still no wiser... anyone know how I can get a memory usage listing from gcc (I'm using msp430-gcc)? I've tried -fmem-report, doesn't not do nowt. Paul Burke

Hello Folks, I am writing what I thought to be a simple application to read and write memory using the ARM JTAG Scan Chain instructions. What...

Hello Folks, I am writing what I thought to be a simple application to read and write memory using the ARM JTAG Scan Chain instructions. What I am finding is that I can read and write registers without issue but whan I try to use system speed instructions (as required) to do the memory accesses - all hell breaks loose. My sequences are simple enough IR SCAN_N DR x10 (scan chain 1) ...

Hello everyone, I'm currently having trouble writing to a dual port block memory generated with the IP (Core Generator) from WebPack, I'm using...

Hello everyone, I'm currently having trouble writing to a dual port block memory generated with the IP (Core Generator) from WebPack, I'm using the Spartan 3E development board. I generated a dual port block memory intending to use one port for write only (no read on write) and the other port for read only. I'm able to read data when loading an init file (I loaded this file just for testing p...

Hello, I am about to use a P89c669 in a design with external program memory. Problem is that the manual states that EA pin either disables...

Hello, I am about to use a P89c669 in a design with external program memory. Problem is that the manual states that EA pin either disables external program memory when held HIGH, or disables internal flash when EA is held LOW. The feedback I got from Philips is that when EA is held HIGH (???) both external and internal memory can be used in a mixed mode. So the big question is, if I wan...

Hi, I am confronted with the followig problem: we are building devices with 8-bit cpus and about 128 K EPROM (banked) and 16 K RAM. They have...

Hi, I am confronted with the followig problem: we are building devices with 8-bit cpus and about 128 K EPROM (banked) and 16 K RAM. They have been working since many years flawlessly. Now we get sometimes reports from customers about mysterious failures. These failures seem to be caused by wrong memory contents, i.e. there are single bits flipped, sometimes from 0 to one, sometime from ...

Hi all, I am trying to erase memory blocks of the flash mem. above the code sections. Those regions are accessable with BBR only, and my...

Hi all, I am trying to erase memory blocks of the flash mem. above the code sections. Those regions are accessable with BBR only, and my window is address range 0xD000 to 0xDFFF. It just happens that Zilog BBRs match some of the M29F010 memory blocks. So BBR[0]=0xF, address=0xD000 means 0x1C000, or in Flash mem blocks is block number 7 that covers a region of 0x1C000 to 0x1FFFF. Now,...

Hi, I've a question on how blocks are mapped from memory to a set-associative cache. Let's say, the instructions in memory are all 32 bits...

Hi, I've a question on how blocks are mapped from memory to a set-associative cache. Let's say, the instructions in memory are all 32 bits long, the I-cache (16kByte) is 2-way set-associative and the each cache line is 256 bits wide (so each line can hold 8 instructions). How will the instructions be mapped into the sets? Let's say the first 8 instructions from memory are mapped int...

Do different NAND memory manufacturers have different programing algorithims... such that replacing one manfucaturer with another means the...

Do different NAND memory manufacturers have different programing algorithims... such that replacing one manfucaturer with another means the flash programming algorithims must be changed in bootloaders etc. IE changing say both manufacturer and size of flash. I look forward to your comments. Joe