Address Mapping LPC24XX

Started by Mad I.D. in comp.arch.embedded11 years ago 1 reply

I just connected a 32MB of x32 SDRAM (one IC) on LPC2478 chip and unfortunately have some doubts. SDRAM Spec: 4k Row (12bits) x 512 column...

I just connected a 32MB of x32 SDRAM (one IC) on LPC2478 chip and unfortunately have some doubts. SDRAM Spec: 4k Row (12bits) x 512 column (9bits) x 32 bits. I was having trouble to figure out where to connect bank address pins and found in some other document (not user manual) that A14:A11-> BA1:BA0 should be OK. Why is this not documented in user manual? Did I miss something ? [A12 is


Trace length for SDRAM lines?

Started by Not Really Me in comp.arch.embedded13 years ago 4 replies

How important is the trace length balance on signal lines to SDRAM? I recall coming across a document saying that the trace lengths needed to...

How important is the trace length balance on signal lines to SDRAM? I recall coming across a document saying that the trace lengths needed to have less than .5 inch difference from shortest to longest. But I think that was a DDR2 doc. I see some very obvious S curves in the lines on an Atmel SAM9261 EK board that uses PC100 speed SDRAMS. We will be using similar parts on a new des...


Problem with SDRAM Memory

Started by Giuseppe Monteleone in comp.arch.embedded14 years ago 1 reply

Hi All I have some problem with SDRAM memory interface. I'am using a SHARP LH79525 ARM controller. when i give a precharge command i see...

Hi All I have some problem with SDRAM memory interface. I'am using a SHARP LH79525 ARM controller. when i give a precharge command i see with a logical analyzer a wrong comand WE=L CS=L RAS=H CAS=L A10=H whitch seem to be a write command There are some configuration that can take a write command as precharge ? Thanks Ing Giuseppe Monteleone


at91rm9200 Board gets reset spontaneously

Started by Mayank Kaushik in comp.arch.embedded15 years ago 2 replies

Hi , Im trying to build a Development board for the AT91RM9200 and am using SDRAM in 16 bit mode , and 2 Mb Flash. I have managed to Store...

Hi , Im trying to build a Development board for the AT91RM9200 and am using SDRAM in 16 bit mode , and 2 Mb Flash. I have managed to Store U-boot in the Dataflash and to get it to boot from it. The Atmel Utility picks up U-boot from the Flash and runs it from SDRAM. The problem im having is that spontaneously while running , the System automatically Resets. This was not happening prior ...


Yet another SDRAM init request - MT48LC4M32B2 on MCF5329

Started by ahunsdon in comp.arch.embedded10 years ago

Sorry guys - I know this an old subject but I am having problems and need your help. MCF5329 Coldfire processor (80Mhz) interfacing to...

Sorry guys - I know this an old subject but I am having problems and need your help. MCF5329 Coldfire processor (80Mhz) interfacing to MT48LC4M32B2 SDRAM. New design loosely based on the EVB reference. Started with the config from the 5329 EVB board and tweaked from there. Works OK with byte/word access but seems to "lock up" completely with long word access. and with LCD display enab...


Put method in specific memory

Started by Tom in comp.arch.embedded16 years ago 8 replies

Hi, I was wondering if it is possible to put a certain method in your program in a specific memory ? For example, I have a slow sdram...

Hi, I was wondering if it is possible to put a certain method in your program in a specific memory ? For example, I have a slow sdram and a fast ddr ram available. I want the ddr ram to contain a fft method, all other code should be stored in the sdram... Can this be done with linker scripts ? Thanks, Tom


interrupt vector on pxa255

Started by Jacek in comp.arch.embedded14 years ago 1 reply

Hi all, could help me to understand how to relocate interrupts on the pxa255 processors? The arm architecture has the interrupt vector at...

Hi all, could help me to understand how to relocate interrupts on the pxa255 processors? The arm architecture has the interrupt vector at 0x0 or 0xFFFF0000 address. How to place the interrupt vector in the SDRAM memory while this procesor has the SDRAM memory placed at 0xa0000000. I tryed to understand the uboot start code and other loaders but they have the interrupt vector placed at...


MPC8641D (dual e600 core) memory latency?

Started by Joseph H Allen in comp.arch.embedded13 years ago 6 replies

Does anyone know what the SDRAM memory latency is going to be for this new embedded controller chip? Latencies on past PPCs were abysmal (~280...

Does anyone know what the SDRAM memory latency is going to be for this new embedded controller chip? Latencies on past PPCs were abysmal (~280 ns for MPC7447 1.4 GHz with Marvell Discovery memory controller). I'm hoping the MPC8641D does better with its on-chip memory controller. It would be nice if the latency approached the SDRAM tRC, like modern x86s. -- /* jhallen@world.std.com A...


AT91RM9200 and 16-bit SDRAM not working

Started by Stef in comp.arch.embedded15 years ago 13 replies

Hello All, I am trying to get a 16-bit SDRAM (MT48LC16M16A2-75) to work with the AT91RM9200 and no matter what I try, it fails to work...

Hello All, I am trying to get a 16-bit SDRAM (MT48LC16M16A2-75) to work with the AT91RM9200 and no matter what I try, it fails to work properly: Hardware connections: AT91RM9200 MT48LC16M16A2 ---------- ------------- D0-15 DQ0-15 A2-A11 A0-A9 SDA10 A10 A13-A14 A11-A12 BA0/1 BA0/1 SDCKE CKE SDCK CLK \BS0/1 DQML/H \RAS \RAS \...


CPU with SDRAM, USB, MAC, CAN, ADC and PWM ?

Started by Vladimir Vassilevsky in comp.arch.embedded10 years ago 6 replies

Is there such CPU that has SDRAM controller, USB host/slave, Ethernet MAC, CAN as well as utility ADC and several PWM channels all in one...

Is there such CPU that has SDRAM controller, USB host/slave, Ethernet MAC, CAN as well as utility ADC and several PWM channels all in one chip? The performance is not very critical; lower cost is important. There are plenty of choices that have either (Ethernet + USB) or (ADC + PWM), but it looks like none of them have both. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant ...


Memory choices

Started by Joe G (Home) in comp.arch.embedded11 years ago

Hi All, I am developing a ARM9 system, The ARM9 has an external memory controller on board. I am facing some choices in memory as the...

Hi All, I am developing a ARM9 system, The ARM9 has an external memory controller on board. I am facing some choices in memory as the memory controller can use SDR SRAM and DDR SRAM , as well as other features. Can comment on the following choices (price and availability, popularity) SDRAM (512Mbyte total) SDR or DDR SDRAM ? Data width x8 x16 x32? NAND Flash (128Mbyte...


SDRAM data bus width & linux

Started by solarst in comp.arch.embedded11 years ago 4 replies

Due to space limitations, our small embedded system (whicih uses a Samsung S3C2440A processor) uses one SDRAM chip. The address bus is 32 bits,...

Due to space limitations, our small embedded system (whicih uses a Samsung S3C2440A processor) uses one SDRAM chip. The address bus is 32 bits, but the data bus is only 16 bits. Is there a special option we can configure on Linux so it knows to use a 16-bit data bus? Similarly, are there options for bootloaders such as vivi or U-boot to specify usage of a 16-bit data bus with a 32-bit address? ...


cutting down opb_clk cycles while read-write BRAM-DDR in FPGA

Started by chakra in comp.arch.embedded11 years ago 1 reply

Hello all, I am working on a project which involves a simple BRAM, OPB-PLB, Microblaze/PPC, and opb_ddr_sdram controller. I am reading 1280...

Hello all, I am working on a project which involves a simple BRAM, OPB-PLB, Microblaze/PPC, and opb_ddr_sdram controller. I am reading 1280 bytes of data from bram (32 bits each read, thus a total of 320 reads) and writing it to DDR sdram. i am using Xilinx standalone OS. i use the command XIo_in32(addr) to read from bram and use XIo_out32(addr,data) to write to DDR sdram controller. h...


files on YAFFS file system

Started by KIRAN in comp.arch.embedded10 years ago

Hi All, I am writing a media player for my target. I was able to write it on windows and I did easy porting of the same to my target device....

Hi All, I am writing a media player for my target. I was able to write it on windows and I did easy porting of the same to my target device. Now the problem is the file system. I have YAFFS mounted on SDRAM. I need some media file for my player to play. But my file system on SDRAM contains 0 files (as expected). As there any way to get the media file linked the target image so that the med...


External SPI Flash for storing data

Started by pozz in comp.arch.embedded11 months ago 15 replies

I have a board with Cortex-M3 NXP LPC1875 MCU with 512kB internal Flash, one 8MB external SDRAM and 2MB external SPI Flash. The external Flash...

I have a board with Cortex-M3 NXP LPC1875 MCU with 512kB internal Flash, one 8MB external SDRAM and 2MB external SPI Flash. The external Flash is connected to a normal SPI, not SPIFI (in other words, it isn't mapped to the internal address space). Insted the SDRAM is mapped to the internal address space, starting from address 0xA000 0000. The application will use a 480x272 RGB LCD conne...


Is there any good arm9 chip contains excellent float multiple performance?

Started by Readon Shaw in comp.arch.embedded14 years ago 6 replies

A full functional SOC is prefered, LCD controller, A/D, PS/2 keyboards & mouse, SDRAM, etc. Any suggestion?

A full functional SOC is prefered, LCD controller, A/D, PS/2 keyboards & mouse, SDRAM, etc. Any suggestion?


how can we access sdram from atmel 8051

Started by gaus in comp.arch.embedded13 years ago 2 replies

hello ......... can some buddy explain me the programming to access the sd ram throgh 8051 its very urgent........please tell me...

hello ......... can some buddy explain me the programming to access the sd ram throgh 8051 its very urgent........please tell me ...................or give the solution in my email id g.gaurav.s@gmail.com


PXA270 Development board

Started by Anonymous in comp.arch.embedded15 years ago 2 replies

Hello, I am looking for a PXA270 based board with 128MB SDRAM,PS/2 mouse and keyboard ports, CF slot and a working linux port. I am trying to...

Hello, I am looking for a PXA270 based board with 128MB SDRAM,PS/2 mouse and keyboard ports, CF slot and a working linux port. I am trying to build a web browsing station. Thanks for your suggestions. Kanchan


linux dies on custom at91rm9200 board

Started by amstewa2 in comp.arch.embedded14 years ago 1 reply

Hello all Im trying to get linux up and running on my system. I have 16MB of SDRAM at 0x20000000 and 2MB of dataflash. I've started with the...

Hello all Im trying to get linux up and running on my system. I have 16MB of SDRAM at 0x20000000 and 2MB of dataflash. I've started with the at91rm9200dk files in the kernel as my start point, and I can get it to boot if and only if I disable my dCache. Im imaging there is a setting somewhere Im over looking that is still trying to map the caches with 32MB of ram (which the dk has) but I ha...


Verilog modeling.

Started by Artem in comp.arch.embedded15 years ago 1 reply

Hi all. I have a "Verilog Behavioral Model of Synchronous 128M SDRAM". I have a Quartus II. How I can use this model in this software? I have...

Hi all. I have a "Verilog Behavioral Model of Synchronous 128M SDRAM". I have a Quartus II. How I can use this model in this software? I have read in manual that verilog simulation is not supported by quartus.