EmbeddedRelated.com

Linux on Capio II (Geode) ?

Started by Phil in comp.arch.embedded20 years ago 5 replies

Hi all. Has anyone run Linux from the Disk-on-Chip on these little beasts? Bought 11 of them for about $2 apiece. They have 2xUSB, sound,...

Hi all. Has anyone run Linux from the Disk-on-Chip on these little beasts? Bought 11 of them for about $2 apiece. They have 2xUSB, sound, e100 ethernet, 16MB DOC, 64MB 144 pin SODIMM SDRAM. I have a Rocky 558EV SBC running SuSE 9.0 with DOC socket to transfer OS images, but even with all DOC support compiled into the SuSE 2.4.21 kernel, fdisk, dd, mkfs, etc. seem to freeze up when access...


PCI bus controller?

Started by David Huseby in comp.arch.embedded20 years ago 10 replies

Does anybody know of any good PCI bus controllers that are suitable for use hobby boards. I've been thinking about designing a fully fledged PC...

Does anybody know of any good PCI bus controllers that are suitable for use hobby boards. I've been thinking about designing a fully fledged PC using a ColdFire chip with SDRAM, PCI, USB and IDE. Getting Linux up and running shouldn't be a problem if I use common USB and PCI chips. Any suggestions and sources for nice PCI bus controllers? Dave


Regarding calculation of free memory

Started by ssubbarayan in comp.arch.embedded18 years ago 62 replies

Gurus, I was just wondering what could be the best possible way to calculate free memory while our code is running in SDRAM.I have used vxworks...

Gurus, I was just wondering what could be the best possible way to calculate free memory while our code is running in SDRAM.I have used vxworks and it uses a approach to calculate the free memory as follows: Fill up the entire stack with 0xeeeee and then when you start using the stack,if at all a particular address in memory is used,the value of 0xeeeee in that location should be overwritten...


Looking for 1G NAND Flash

Started by Joseph Goldburg in comp.arch.embedded14 years ago 4 replies

Hi All, I'm looking for reliable sources of 1G NAND flash x16 preferred but can accept x8 BGA preferred but can accept TSOP, TSSOP 3V,...

Hi All, I'm looking for reliable sources of 1G NAND flash x16 preferred but can accept x8 BGA preferred but can accept TSOP, TSSOP 3V, 3v3 volt preferred but may be able to accpet 1v8. qty ~ 8k PA Do you have any suggested MFG's and suggested part No's that may fit the requirement? It seems that NAND and SDRAM see to be quite market volatile Thanks in advance Regs Joe ...


LH79520 interrupt problem

Started by Anonymous in comp.arch.embedded17 years ago 2 replies

hi, I'm using a custom designed board having LH79520 with 32MB micron SDRAM & 8MB flash. Very similar to LogicPD board, but without the extras...

hi, I'm using a custom designed board having LH79520 with 32MB micron SDRAM & 8MB flash. Very similar to LogicPD board, but without the extras (lan, audio, CPLD, buffers etc). It does have a external reset chip. The board works fine when no interrupts are used. However, when I try to use the timer interrupt, it works intermittently between power-ups. Meaning, the interrupt is working afte...


Question about the speed of SPI RAM

Started by Like2Learn in comp.arch.embedded13 years ago 15 replies

Hi there, We found we had to add an external RAM (SRAM or SDRAM) at the late stage of electrical design. Basically there are only 2 GPIO pins...

Hi there, We found we had to add an external RAM (SRAM or SDRAM) at the late stage of electrical design. Basically there are only 2 GPIO pins still available, otherwise the RAM has to share with other peripherals, such as SPI and I2C. I prefer to connect the external RAM with SPI bus. However, I am not sure if it is fast enough for RAM read/write. Does anybody know the typical speed of SPI...


External SPI Flash for storing data

Started by pozz in comp.arch.embedded4 years ago 3 replies

Maybe someone remember the thread[1] that I created some months ago. I was searching a simple way to save on the external SPI Flash some...

Maybe someone remember the thread[1] that I created some months ago. I was searching a simple way to save on the external SPI Flash some constant data (mainly bitmaps) and copying them to SDRAM at startup. I finally put my hands on that project again and I think I've found a good solution. The MCU (LPC1785 from NXP) has an internal Flash memory starting from 0x0000 0000 and an extern...


Unable to boot Kernel on ARM after Memory Remap

Started by sg83 in comp.arch.embedded16 years ago 1 reply

Hi everyone, I've been working with an imx27ads from Freescale. The BSP from Freescale includes a Redboot that contains the following memory...

Hi everyone, I've been working with an imx27ads from Freescale. The BSP from Freescale includes a Redboot that contains the following memory map: Phys | Virtual | Enabled|Type 0xA0000000-0xA7FFFFFF| 0x00000000-0x07FFFFFF| Yes |SDRAM 0xD6000000-0xD6FFFFFF| 0xD6000000-0xD6FFFFFF| No |SRAM I've managed to enable the SRAM (verified by loading kernel to it...


Looking for a tools to report memory usage

Started by Like2Learn in comp.arch.embedded13 years ago 14 replies

I have a legacy embedded product written by C under IAR workbench. I want to know how much memory the program will consume on-the-fly, so I can...

I have a legacy embedded product written by C under IAR workbench. I want to know how much memory the program will consume on-the-fly, so I can decide a suitable size of SDRAM for it, not too small to affect the performance, while not too big to affect the BOM. I don't have IAR workbench installed yet. Is there any tool that can help me to estimate the memory usage of a program even without...


OV9653 image sensor interface problems

Started by swami in comp.arch.embedded16 years ago 2 replies

Hi, I am trying to capture the a single frame through omnivision 9653 and trying to write in sdram of ceva dsp processor.(i am new to this...

Hi, I am trying to capture the a single frame through omnivision 9653 and trying to write in sdram of ceva dsp processor.(i am new to this area) i followed the sccb protocol for communication(read/write) and the default values of the registers are read correctly.i can also be able to modify the ov9653 registers and the values are reflected back.so far ok for capturing the image (SXGA - 1280x1...


gcc ld and bss sections on SDRAM

Started by pozz in comp.arch.embedded2 years ago 4 replies

My platform is LPC546xx, Cortex-M4 by NXP, and the build environment is based on GCC ARM toolchain (MCUXpresso IDE). However the question is...

My platform is LPC546xx, Cortex-M4 by NXP, and the build environment is based on GCC ARM toolchain (MCUXpresso IDE). However the question is generic. The default linker script instructs linker to put bss sections (zero initialized data) in internal RAM. During startup, before main, bss sections, described in a table on Flash, are reset to zero: __attribute__ ((section(".after_vecto...


Jave on Embedded Linux

Started by moti...@gmail.com in comp.arch.embedded18 years ago 15 replies

I have an embedded system and want to set J2SE or J2ME on Embedded Linux. I heard a few ways to install JDK but I cound not understand...

I have an embedded system and want to set J2SE or J2ME on Embedded Linux. I heard a few ways to install JDK but I cound not understand becase, didn't have fully information. I consider about kaffe and blackdown package, I could not build that, however. My embedded system's hardware specification Processor : Intel PXA255 400MHz SDRAM : Samsung 64 MB Flash : Intel strata flash 32 MB Et...


deciding capacitor & resistor values

Started by Kshitiz Bartariya in comp.arch.embedded10 years ago 4 replies

I am new to schematic design and studying OLinuXino A10s schematics. A generic question : How do we decide the resistor & capacitor values...

I am new to schematic design and studying OLinuXino A10s schematics. A generic question : How do we decide the resistor & capacitor values required to interface multiple ICs on a pcb ? E.x. I am unable to understand why a 22ohm resistor is present in the clock signal (SCK,SCK# pins - W2, Y1 ) from A10s to SDRAM (h5tq2g83cfr-h9c) (CK, CK# pins - F7, G7). It is not given in either of their da...


Dma stalling!

Started by adonis in comp.arch.embedded17 years ago 6 replies

I am using a ADSP blackfin Bf533 processor, i have only sport Rcv and Sport Tx Dma configured for ethernet rcv and tx respectively. I run...

I am using a ADSP blackfin Bf533 processor, i have only sport Rcv and Sport Tx Dma configured for ethernet rcv and tx respectively. I run a loopback code to loop packets from sport Rcv to Sport TX (with an intermediate SDRAM copy). Sport Tx dma often stalls and leads to a dma stuck up condition. things i have observed: ----------------------------- (i) DMA stuck up does not occur if inter...


USB OTG on ARM7 based MCU

Started by Mad I.D. in comp.arch.embedded15 years ago 18 replies

Hello all. I'm designing a system running on (ex Sharp) LH79520 NXP MCU with ARM720T core. I'm currently adding USB OTG function but there...

Hello all. I'm designing a system running on (ex Sharp) LH79520 NXP MCU with ARM720T core. I'm currently adding USB OTG function but there is something bothering me. By now, my system already has x32 SDRAM and x16 FLASH memory. I've done a lot of research about OTG controllers available on the market and picked NXP ISP1362 "Single-chip Universal Serial Bus On-The-Go Controller". It's a mem...


Is this ARM possible?

Started by ghazanhaider in comp.arch.embedded17 years ago 8 replies

I'm looking for this chip: ARM920 or ARM926. NOT in BGA format (TQFP or LQFP) SDRAM controller LCD controller able to drive at least 320x200...

I'm looking for this chip: ARM920 or ARM926. NOT in BGA format (TQFP or LQFP) SDRAM controller LCD controller able to drive at least 320x200 color. Most ARM9 chips are either BGA or does not have an LCD controller. The LCD interface requires many more pins but I'm sure the maximum of 208 pins can include all the important ARM9 pins plus an LCD bus. I do not need many GPIO pins and 16-b...


OSE5.1/PPC405 memory layout constraints?

Started by Florian Boelstler in comp.arch.embedded18 years ago 3 replies

Hi, I was wondering whether there are any PPC405-specific memory layout constraints. I am trying to get OSE5.1 (some embedded RTOS)...

Hi, I was wondering whether there are any PPC405-specific memory layout constraints. I am trying to get OSE5.1 (some embedded RTOS) running on a PPC405 embedded system. It went well on a dedicated evaluation board (Memec VP20, VirtexII-Pro), but "moving" to the target system failed so far. There is a 32MB SDRAM located at 0xFC000000 - 0xFDFFFFFF. The OS is configured to use that me...


DDR SDRAM with Xilinx Virtex 2 on self designed PCB

Started by Elmo in comp.arch.embedded19 years ago 3 replies

Hello, last week I started the development and design of a PCB with an FPGA (Xilinx Virtex 2) and two DDR-SDRAMs in parallel. No big deal, I...

Hello, last week I started the development and design of a PCB with an FPGA (Xilinx Virtex 2) and two DDR-SDRAMs in parallel. No big deal, I thought, keeping in mind the most obvious design rules, i.e. combining the adress lines and separating the data and strobe (DQS) lines. But now I came across the many other signals there are, e.g. the clock signals, S0 and S1, CAS, RAS, WE, etc. My fi...


Programming AMD type Nor flash.

Started by JY Kim in comp.arch.embedded17 years ago 3 replies

I am working with samsung s3c2410 and ST M29W320T flash. The flash is AMD type Nor. I am using trace32 and going to check flash interface. As...

I am working with samsung s3c2410 and ST M29W320T flash. The flash is AMD type Nor. I am using trace32 and going to check flash interface. As far as I heard, to check flash interface one should download file. not just assigning value like checking SDRAM. Please let me know site or information on how to do this or trace32 cmm file. Please answer Thanks.


AT91RM9200 it's easy to broke data lines ?

Started by Pelos in comp.arch.embedded17 years ago

Hi, I'm going to run my board with AT91RM9200. My board has 32bit SDRAM (2 x HY57V561620C) data bus width. I saw that some data lines was tied...

Hi, I'm going to run my board with AT91RM9200. My board has 32bit SDRAM (2 x HY57V561620C) data bus width. I saw that some data lines was tied together D24 D25 and D26 (close to CPU). I reworked them - now looks clear (I checked contacts too) but my memory test shows that lines D24 and D25 are still high. So my question is - Is it Atmel so fragile ? Could I broke it ? Here is part of m...