Underclocking ARM and SRAM

Started by ghazanhaider in comp.arch.embedded13 years ago 14 replies

I have an LPC3180 header board that needs 10MHz+ crystals to run per spec. I plugged in a ~2MHz crystal and it ran, as slow as expected. I've...

I have an LPC3180 header board that needs 10MHz+ crystals to run per spec. I plugged in a ~2MHz crystal and it ran, as slow as expected. I've underclocked PIC parts down to being static, even using a button as a clock. Can this be done with ARM MCUs? Can this be done with ARM MCUs interfaced with SRAM chips?


RCHW for powerpc MPC5566

Started by matrix13 in comp.arch.embedded8 years ago 1 reply

Hello Community, I am new to PowerPC and I have the Freescale MPC5566EVB with me for experimenting with MPC5566. I am using CodeWarrior with...

Hello Community, I am new to PowerPC and I have the Freescale MPC5566EVB with me for experimenting with MPC5566. I am using CodeWarrior with PENexus Micro debugger. My aim is to develop a code for FMPLL and store it in MPC internal SRAM. Then I want to boot the device from the internal SRAM. I have two questions regarding this. 1. What is the configuration of BOOTCFG for booting from 'interna...


Mixing 12 nS memory with 15 nS memory

Started by D. Zimmerman in comp.arch.embedded16 years ago 4 replies

I have a Zilog development system (the Acclaim) and I need to add some SRAM. I'm running into a lot of problems finding 3 pcs. of 12...

I have a Zilog development system (the Acclaim) and I need to add some SRAM. I'm running into a lot of problems finding 3 pcs. of 12 nS, 512K x 8 memory, so I would like to know if anyone has had problems mixing 12 nS with 15 nS SRAM. It looks like 15 nS memory should work because there is an added cycle (20 nS) anyway, but I'm hesitant to go forward unless I know that t...


WTB 2MB SRAM Linear memory pcmcia card (or trade)

Started by Anonymous in comp.arch.embedded15 years ago 2 replies

I am looking for a 3.3 volt, 2 meg SRAM memory card. I have a 2MB Smart Technologies Flash card but I think it behaves like a HDD and I just...

I am looking for a 3.3 volt, 2 meg SRAM memory card. I have a 2MB Smart Technologies Flash card but I think it behaves like a HDD and I just need a card that can be accessed as plain-ole-memory. Thanks heirbrande at the yahoo at the dot at the com


Flash DOC to NV SRAM

Started by S. Harnek in comp.arch.embedded16 years ago 3 replies

Hi folks, I have a evaluation SBC (the LogicFlex from jkmicro http://www.jkmicro.com/technicalinfo/ti_logicflex.html ) with a 8 MB...

Hi folks, I have a evaluation SBC (the LogicFlex from jkmicro http://www.jkmicro.com/technicalinfo/ti_logicflex.html ) with a 8 MB Flash DOC. Would anyone know whether a NV SRAM, capacity 4 MB to 8 MB, could be plug compatible, i.e. plug in and go ? I am not an embedded specialist (a systems integrator/ tinkerer who manages to solder a little with only the occasional finger singed )


8051 - SRAM interface problem

Started by andrew queisser in comp.arch.embedded16 years ago 2 replies

I've successfully interfaced a single 32K SRAM chip to a T89C51RD2. The CE pin is connected to the A15 line (P2.7) on the 8051. Happily...

I've successfully interfaced a single 32K SRAM chip to a T89C51RD2. The CE pin is connected to the A15 line (P2.7) on the 8051. Happily unencumbered by any real digital design expertise I decided to piggy-back a second 32K chip (62256) onto the first one and add an inverter between the two CE lines. In theory only one of the chips should get selected now. However, the memory test fails ...


Low power memory

Started by ghazanhaider in comp.arch.embedded13 years ago

I posted about this issue a year ago, just revisiting. I've been looking for the lowest power any external memory chip can dissipate per...

I posted about this issue a year ago, just revisiting. I've been looking for the lowest power any external memory chip can dissipate per megabyte and access speed. Low power SRAM is the first choice, but the estimated power for a constant series of bursts gets very expensive on power. Async SRAM takes longer to return, but should allow lower power. I've seen some nice PSRAM chips at re...


Unable to boot Kernel on ARM after Memory Remap

Started by sg83 in comp.arch.embedded12 years ago 1 reply

Hi everyone, I've been working with an imx27ads from Freescale. The BSP from Freescale includes a Redboot that contains the following memory...

Hi everyone, I've been working with an imx27ads from Freescale. The BSP from Freescale includes a Redboot that contains the following memory map: Phys | Virtual | Enabled|Type 0xA0000000-0xA7FFFFFF| 0x00000000-0x07FFFFFF| Yes |SDRAM 0xD6000000-0xD6FFFFFF| 0xD6000000-0xD6FFFFFF| No |SRAM I've managed to enable the SRAM (verified by loading kernel to it...


Silicon Bug?

Started by Robert Higgins in comp.arch.embedded9 years ago 2 replies

I've run into a problem with a little project I've been working on. The project is a flash loader utility for the TMS470 that runs from RAM and...

I've run into a problem with a little project I've been working on. The project is a flash loader utility for the TMS470 that runs from RAM and programs the flash with data coming in over a serial port. The micro is a TMS470R1A288, which is based on an ARM7TDMI core. There is 16K of on-chip SRAM starting at address 0x00400000; the flash loader code runs entirely from this SRAM. The flash l...


linking imagecraft compiler with assember file

Started by fabrizio in comp.arch.embedded16 years ago 5 replies

Hi, I am using the IMAGECRAFT compiler to program the ATMEGA16 device. I'm trying to write a PC program, using Delphi, to make a monitor...

Hi, I am using the IMAGECRAFT compiler to program the ATMEGA16 device. I'm trying to write a PC program, using Delphi, to make a monitor that will be able to manipulate SRAM memory on the ATMEGA16 device. The PC is connected via RS232 to the Device. For example: Command entered on the PC : D 0060 10 Meaning: Display 10H Bytes starting from SRAM address 0060H ...


microcontroller for simple audio project

Started by ethan in comp.arch.embedded15 years ago 17 replies

hi, i'm looking for a uC for a simple portable audio project. the basic specifications i'm looking for are: - 8/16 bit datapath - hardware...

hi, i'm looking for a uC for a simple portable audio project. the basic specifications i'm looking for are: - 8/16 bit datapath - hardware multiply (8x8 ok, more bits the merrier) - 20+ MHZ instruction execution - onboard flash/SRAM (8kbytes+ FLASH, 1kbyte+ SRAM) - UART - onboard DAC (mono ok, stereo better) - free build tools - cheap! right now i'm looking at the SI Labs C8051F330....


Netsilicon - Net + 50 hardware prob

Started by bdutta in comp.arch.embedded12 years ago

Hi All, I am facing problem when debugging Net+50 board (developed by us). It is showing download ok. but prog not running perfectly. It is...

Hi All, I am facing problem when debugging Net+50 board (developed by us). It is showing download ok. but prog not running perfectly. It is going to exception vector add. But the same prog running on Demo board. In our board we are using SRAM (128K X 16). I had made nec. modification for SRAM in MMCR & CSBAR. It is not going to reset_handler routine after reset. Is this prob due to the size ...


LPC2470 - SDRAM does not work

Started by Matej755 in comp.arch.embedded11 years ago 1 reply

Hi, my design "sample board" is connecting LPC2470 via 32 bit bus SRAM and SDRAM memory. SRAM works very well but SDRAM does not work. I use 2...

Hi, my design "sample board" is connecting LPC2470 via 32 bit bus SRAM and SDRAM memory. SRAM works very well but SDRAM does not work. I use 2 devices WINBOND W9816G6IH, 512Kx2Banksx16bits. I need urgenly help somebody... how to setting EMC and init SDRAM to start works. SDRAM gets eror reading data after write. I thing init procedure is no right. Thank you.


Nintendo Revolution will use MoSys 1T-SRAM. my thoughts

Started by nintendog in comp.arch.embedded15 years ago 12 replies

http://gc.advancedmn.com/article.php?artid=4846 (read the article there, it is *not* pasted below) Revolution is apparently going to be...

http://gc.advancedmn.com/article.php?artid=4846 (read the article there, it is *not* pasted below) Revolution is apparently going to be released in mid 2006. it will be using MoSys 1T-SRAM for memory, like the Gamecube. it seems that Elpida lost out on the Revolution RAM deal. Elpida is a major provider of RAM. they're one of the RAM providers of Rambus XDR memory for the upcoming P...


Omnivision OV7640 SCCB (I2C?) bus problem

Started by Anonymous in comp.arch.embedded14 years ago 25 replies

Hello, I am hoping someone can assist me with the SCCB (I2C?) bus of an Omnivision OV7640 image sensor. I am unable to get the OV7640 to...

Hello, I am hoping someone can assist me with the SCCB (I2C?) bus of an Omnivision OV7640 image sensor. I am unable to get the OV7640 to respond to commands on the SCCB bus. Preliminary : I have connected the OV7640 to a SRAM, and feed VSYNC and HREF to an Altera 7032S CPLD which controls and address counter and the SRAM. I can successfully capture an image frame, and transfer it (...


Memory choices

Started by Joe G (Home) in comp.arch.embedded11 years ago

Hi All, I am developing a ARM9 system, The ARM9 has an external memory controller on board. I am facing some choices in memory as the...

Hi All, I am developing a ARM9 system, The ARM9 has an external memory controller on board. I am facing some choices in memory as the memory controller can use SDR SRAM and DDR SRAM , as well as other features. Can comment on the following choices (price and availability, popularity) SDRAM (512Mbyte total) SDR or DDR SDRAM ? Data width x8 x16 x32? NAND Flash (128Mbyte...


Program size - Microblaze

Started by Yannick in comp.arch.embedded12 years ago 6 replies

Hi, I want to know the average size of the programs for microblaze (Xilkernel, Uart managment, SRAM managment, Ethernet with Lwip). I think...

Hi, I want to know the average size of the programs for microblaze (Xilkernel, Uart managment, SRAM managment, Ethernet with Lwip). I think that the size of my program is enormous. Even if i choose optimization in compiler option, the program size is too big. My Progam size : 900 ko (My Code, Xilkernel without Lwip) Size of executable.elf Microblaze OPB | - SRAM Contr...


Intel 386EXTC embedded processor "Chip Select"

Started by learner in comp.arch.embedded16 years ago 3 replies

Hi, I am a newbee to this processor and trying to using ChipSelect feature available in this processor. Is the "CHIP Select" unit activated...

Hi, I am a newbee to this processor and trying to using ChipSelect feature available in this processor. Is the "CHIP Select" unit activated only by BIOS. If I connect Flash to UCS and SRAM to CS0 and just load assembly language file in FLASH, is it not possible to use CS? Will I have to load a BIOS telling the processor that CS0 is for SRAM and UCS is for FLASh? Thanks Learner


Problems using Dallas High Speed Micro (89C420) with 74F373 address latch

Started by Anonymous in comp.arch.embedded15 years ago 11 replies

Hi, I'm building an embedded controller that uses the Dallas 89C420 ultra high speed micro with an external 32K SRAM. There's no...

Hi, I'm building an embedded controller that uses the Dallas 89C420 ultra high speed micro with an external 32K SRAM. There's no external program memory - I'm using the internal flash for that. Right now it works just fine at 15Mhz with a 74HC373 address latch and a 70ns SRAM, however I want to run in clock doubled mode at 30Mhz. For this I figure I'll need to use a 74F373 latch instead...


ColdFire M5271 use 52Kb SRAM for C-stack to test DRAM at OS boot ?

Started by alex in comp.arch.embedded14 years ago 1 reply

Hello, Anybody (on any RTOS) on ColdFire M5271 tried to initialize 52Kb SRAM & allocate C-stack there to test (using C-code) DRAM at the boot...

Hello, Anybody (on any RTOS) on ColdFire M5271 tried to initialize 52Kb SRAM & allocate C-stack there to test (using C-code) DRAM at the boot time ? See relevant info I found so far (but there the guy considers allocating stack on DRAM and jumping over it during DRAM test - anybody tried that ?) Newsgroups: comp.os.vxworks Subject: POST / RAM Test Date: 6 Dec 2001 10:20:35 -0800 Fro...