Dear all Here's my problem: I've developed an VHDL IP in ISE and integrate it into a Microblaze peripheral using the "create and import...

Dear all Here's my problem: I've developed an VHDL IP in ISE and integrate it into a Microblaze peripheral using the "create and import peripheral" tool. My IP uses 3 read only and one write only registers to interface with the IPIC module. The IP has one ENB input that must be set to start the operation of the FSM within, and once the IP is running, it sets the RUN output. I have connect...

Hello all, Is there a website or paper that decribes various CPU architectures (i.e. 80x86, 8051, MIPS, ARM...)? I'm looking for pros &...

Hello all, Is there a website or paper that decribes various CPU architectures (i.e. 80x86, 8051, MIPS, ARM...)? I'm looking for pros & cons of various different architectures. I'm planning on coding up my own CPU in VHDL and I want to do a little research before I pick and architecture. Thanks, Eric

Hi, I am a mature student will be doing some complex VHDL and Verilog design work for my course. As well as having to create and test the...

Hi, I am a mature student will be doing some complex VHDL and Verilog design work for my course. As well as having to create and test the functionality of the design (in both languages) I want to document how the design is put together and it's complex hierarchy. Is there anything out there that will allow me to represent my design in some sort of hierarchical functional blocks to us...

Hello, I'm thinking about writing a VHDL 1394b LLC IP. Does anyone know how complicated that task is ? I need it to communicate only with...

Hello, I'm thinking about writing a VHDL 1394b LLC IP. Does anyone know how complicated that task is ? I need it to communicate only with other beta nodes (no legacy nodes, so no border nodes). Moreover I need to use isochronous transfers, so I need to implement the IRM as well. Thanks a lot on advance for any suggestion, Marco

Does anybody have a link to VHDL code to transform say... XC9572 & CY7C1399 into a 'slow' Dual 16Kx8 FIFO (for about $3.65 in Qty 100) IDT's...

Does anybody have a link to VHDL code to transform say... XC9572 & CY7C1399 into a 'slow' Dual 16Kx8 FIFO (for about $3.65 in Qty 100) IDT's stuff is too $$$$ and I don't really need the 'instantaneous' simultaneous access from "both sides"... handshaking with ready/done deal is good enough.

Is there currently a high speed (480Mbs) USB 2.0 general IO board available anywhere? Perhaps one using an FPGA? I know there is a vhdl...

Is there currently a high speed (480Mbs) USB 2.0 general IO board available anywhere? Perhaps one using an FPGA? I know there is a vhdl design finished on opencores.org, but I did not see a mention of anyone producing the actual physical device. Thanks, Rick

dear I am looing for open source or publicly available source code (in HDL) of crossbar switch for learning purpose. Simple implementation,...

dear I am looing for open source or publicly available source code (in HDL) of crossbar switch for learning purpose. Simple implementation, Part of the code, some hints, some guidance will be nice for me. Could anyone help me with this?

Good morning,my name is Emad i leave in egypt ,i taken BSC in communication & electronics engineering with GPA "A" an now i preper my master in...

Good morning,my name is Emad i leave in egypt ,i taken BSC in communication & electronics engineering with GPA "A" an now i preper my master in SDR technology.but i don't have any idea to How can i start.i have a strong knowldge in FPGA and VHDL and digital electronics. please advise me how can i start thank you sir and i hope to help me.

Every time I make a minor change to one of my local pcores I have to do a "Clean Netlist" to ensure that the change is carried out. I find this...

Every time I make a minor change to one of my local pcores I have to do a "Clean Netlist" to ensure that the change is carried out. I find this very painful since it then rebuilds all the other IPs. Is there a way I can just compile the changed file? Is it more efficient to use a .vhdl file or a .ngd which I can generate with ISE. Would this save much time?

We want to use the primeview tft lcd (PW045XS1). I looked at the datasheet, but it is very summerary. Does anyone know where I can get more...

We want to use the primeview tft lcd (PW045XS1). I looked at the datasheet, but it is very summerary. Does anyone know where I can get more information or perhaps example code of how to use this lcd. I have to make my own display controller in vhdl, but example code in C would be also helpfull. TIA, Frank

I'm looking for simple VGA (XGA up to 800x600) controller for displaying simple images on the LCD pannel - any suggestion for available ASIC...

I'm looking for simple VGA (XGA up to 800x600) controller for displaying simple images on the LCD pannel - any suggestion for available ASIC (LCD controller) or FPGA (VHDL core) design will do. Thanks, Damir

Hello ! We are an academic institution teaching our students VLSI design, from FPGA to full custom ASIC. We have put great value on...

Hello ! We are an academic institution teaching our students VLSI design, from FPGA to full custom ASIC. We have put great value on teaching VHDL during the past years with very good results from our students. However, we have the impression that these students have difficulties working with schematics as tools to document and express their architectural ideas, in part because we di...

Hi everyone, I was wondering if anyone can point me to some formal method to validate a soft processor core. We have the source code...

Hi everyone, I was wondering if anyone can point me to some formal method to validate a soft processor core. We have the source code (vhdl) and a simulation environment to load programs and execute them, but I'm not sure in this case code coeverage will be sufficient. What about cases like interrupt handling? I can run Dhrystone or CoreMark, but will it be sufficient? Any idea/p...

Hello all, I'm working on the idea/presentation for my next book. It relates to retrogaming from an embedded developer's standpoint (not an...

Hello all, I'm working on the idea/presentation for my next book. It relates to retrogaming from an embedded developer's standpoint (not an emulation book, but more along the lines of "this is how you could develop a modern version of the 2D tile-based graphics ASIC in XYZ old arcade machine", and "this is how you can simulate a YM2159 synthesizer in VHDL"). I feel many of these circuits h...

Hello everyone, I'm working on a project that requires sending pixel data from an fpga to a PC, RS232 would be fine but Ethernet is also...

Hello everyone, I'm working on a project that requires sending pixel data from an fpga to a PC, RS232 would be fine but Ethernet is also considered. (need to create a bit file to process the image in the PC). Any VHDL code reference for the transmission process and any advice on generating the bit file would be highly appreciated. Thanks,

I am trying to write a simple custom IP to get started. I just want to control the LED on my evaluation board. I want to be able to write a...

I am trying to write a simple custom IP to get started. I just want to control the LED on my evaluation board. I want to be able to write a custom IP to prove to myself I am doing it correctly instead of using the IP provided. I am using a Memec V4 UltraController II eval board and EDK 9.1 SP2. I created a template IP using EDK and then wrote my VHDL code to control the LEDs. The proble...

Hello, I am deveolping a VHDL code to get a image from a OV7620 camera. Until now I have managed to get YUV image in a binary file. When I...

Hello, I am deveolping a VHDL code to get a image from a OV7620 camera. Until now I have managed to get YUV image in a binary file. When I display that image the Y component is correct (monochrome image) but the problem is in U and V components. The whole image is all magenta because there isn't green component. I am using CCIR 601 YCbCr color space with formula: R = 1.164(Y ? 16)

I have (just) completed a bachelor in electrical engineering. I have no experience whatsoever in real time/embedded systems but I would like to...

I have (just) completed a bachelor in electrical engineering. I have no experience whatsoever in real time/embedded systems but I would like to move towards this field (embedded control systems) I have a good analog/digital electronics background, plus programming C/C++, computer architecture, VHDL and FPGA, microcontrollers. I am also familiar with general operating system concepts, so I a...

Hi, I am looking at selecting a processor for our SoC platform. Currently we use an embedded 8051 core (small, low power, low...

Hi, I am looking at selecting a processor for our SoC platform. Currently we use an embedded 8051 core (small, low power, low performance, cheap). For our next project, we need more performance, and we are also trying to create a platform suitable for all future projects. The CPU must be available as RTL (VHDL or Verilog) source. Obviously, there are lots of options - Faster 8051 ...

Is there UART in FPGA or whether UART has to be connnect externally..and how can we send information from FPGA through UART to...

Is there UART in FPGA or whether UART has to be connnect externally..and how can we send information from FPGA through UART to Ethernet........can anyone give guidence for writing coding either in VHDL or in Verilog for sending information from FPGA to Ethernet through UART