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Design Doc for Scatter/Gather DMA Engine

Started by balu1303 in comp.arch.embedded15 years ago 1 reply

Hi Mark, This is Balu, a new member in this form, I have read ur Scatter/Gather discussion. It is lot useful for me, actually i want to...

Hi Mark, This is Balu, a new member in this form, I have read ur Scatter/Gather discussion. It is lot useful for me, actually i want to implement a Scatter Gather DMA engine in verilog but I didn't get exactly what will happen inside a Scatter/Gather DAM engine. Can u give any suggestion regarding design or functional diagram of Scatter/Gather DMA Engine. Thanks in advance. Regards, Bal...


Using EDIF file in XPS

Started by yousef_p_m in comp.arch.embedded19 years ago 1 reply

Dear Friends, I have written a verilog code for a module. I have synthesized it with Synplify Pro for a Virtex II Pro chip and it has given me...

Dear Friends, I have written a verilog code for a module. I have synthesized it with Synplify Pro for a Virtex II Pro chip and it has given me an edif netlist file. Now I want to use this synthesized edif file as a peripheral and import it to my system via import peripheral wizard in XPS. but it seems we are not allowed to import an edf file without a top level HDL file. could you please ...


verilog HDL problem

Started by nasi...@gmail.com in comp.arch.embedded17 years ago 1 reply

what is the error in the following code. in it the main module is "test". in that module's "always" block another module "counter" is called....

what is the error in the following code. in it the main module is "test". in that module's "always" block another module "counter" is called. but it shows error. how can i solve the problem? how can i call another module in always block? module counter(clock, reset, count); input clock, reset; output [3:0] count; reg [3:0] next_count,count; always@* begin ...


How to embed Time and Date in Xilinx FPGA?

Started by Anonymous in comp.arch.embedded16 years ago 2 replies

I would like to automatically embed the Xilinx compile (synthesize) time into my FPGA. I have a script file that can put the time and date into...

I would like to automatically embed the Xilinx compile (synthesize) time into my FPGA. I have a script file that can put the time and date into my Verilog code. I would like to automatically call that script file from the Xilinx ISE everytime i run the synthesizer. Is there anyway for the ISE to call an outside routine (other than running the whole thing from a command line without the IS...


Software Defined Radio auf Xilinx Virtex 4

Started by Anonymous in comp.arch.embedded16 years ago 3 replies

Hallo, ich arbeite seit 3 Monaten mit einem Xilinx Ml405 Virtex 4 Board und wollte darauf nun mal ein Software Defined Radio...

Hallo, ich arbeite seit 3 Monaten mit einem Xilinx Ml405 Virtex 4 Board und wollte darauf nun mal ein Software Defined Radio (SDR) implementieren. Ich verstehe alles was auf SDR betrifft (Theorie, Funktionsweise, etc..) ganz gut . Genauso kann ich auch VHDL und VERILOG. Jetzt w=FCrde ich gerne wissen, ob Jemand sich damit auch besch=E4ftigt einem SDR auf oben genanntem Board (oder anderen...