Any *really old* Viewlogic / Xilinx users around here? :)

Started by Peter in comp.arch.embedded14 years ago 1 reply

In the 1990s I used a Xilinx-only version of DOS Viewlogic, version 4 I think. Viewlogic was hacked so that schematic files created in...

In the 1990s I used a Xilinx-only version of DOS Viewlogic, version 4 I think. Viewlogic was hacked so that schematic files created in the unrestricted version could not be opened in the restricted version(s). However, somebody developed a program called sneaky.exe which patched the schematic file, to enable it to be opened. I have been chucking out a large quantity of 5.25" disks with...


Experience with Xilinx Microblaze kit?

Started by larwe in comp.arch.embedded14 years ago 11 replies

I've been asked to write a couple of real-life up-and-running articles about working with the Xilinx PPC/Microblaze kit (ML403 board) consisting...

I've been asked to write a couple of real-life up-and-running articles about working with the Xilinx PPC/Microblaze kit (ML403 board) consisting of a meaty FPGA with PowerPC 405 hard core. I'll have a loaner kit with the option to buy. Has anyone here worked with this kit? The documentation is a bit vague about what exactly comes with the board, software-wise. Specifically: They talk about...


Open-source CableServer for Xilinx Impact on sourceforge.net

Started by Anonymous in comp.arch.embedded13 years ago

Hi All, Here is a open-source CableServer replacement for Impact. Currently Parallel III and Alter ByteBlaster are supported, but any 3rd...

Hi All, Here is a open-source CableServer replacement for Impact. Currently Parallel III and Alter ByteBlaster are supported, but any 3rd party can be implemented easily and can be used from Impact. I've tested only Impact 8.2, if anybody has any problem with 7.1, please let me know! Impact and Xilinx CableServer communication are very pooly written. There is no error recovery at all....


Microblaze and low level interrupt example

Started by Andreas Wassatsch in comp.arch.embedded12 years ago 1 reply

currently i try to write a simple interrupt driven timer example without using the provided help functions in the xilinx edk. The goal is to...

currently i try to write a simple interrupt driven timer example without using the provided help functions in the xilinx edk. The goal is to reduce the code size for a minimal system configuration. The xilinx functions blows up the code, so i try to program the timer and interrupt controller components by my self. So these works, i receive the timer interrupt. My problem is now, that the han...


Xilinx ML403 Board with Monta Vista Linux

Started by EmbeddedBeginner in comp.arch.embedded12 years ago

I've used the files from the Xilinx App Note 925 to get Monta Vista Linux Pro 3.1 on the ML403 board. In the long run I want to be able...

I've used the files from the Xilinx App Note 925 to get Monta Vista Linux Pro 3.1 on the ML403 board. In the long run I want to be able to communicate via the bus with some of the header pins on the board. For now, I am simply trying to send a command or start a program that would light up an LED on the board. How would I even go about this? Thanks,


Kernel image size

Started by Nobby Anderson in comp.arch.embedded10 years ago 6 replies

I've recently upgraded a ppc405 build for a Virtex 4 device from kernel 2.6.15 (arch/ppc) to 2.6.31 (arch/powerpc) and the size of the image has...

I've recently upgraded a ppc405 build for a Virtex 4 device from kernel 2.6.15 (arch/ppc) to 2.6.31 (arch/powerpc) and the size of the image has increased from about 900k to 1.4M. As far as I can tell I've pretty much the same config options set. The 2.6.15 kernel was straight from the kernel mainline with some xilinx drivers hacked in, the .31 is straight from git.xilinx.com with nothing ...


RoseRT + Threadx + Xilinx Microblaze

Started by Roel in comp.arch.embedded15 years ago 1 reply

Hi, I would like to develop software by means of RoseRT, and running it using the ThreadX OS and a Xilinx Microblaze softcore. There seems to...

Hi, I would like to develop software by means of RoseRT, and running it using the ThreadX OS and a Xilinx Microblaze softcore. There seems to be a Target Adaptation Layer for ThreadX available for RoseRT and there is a ThreadX version of Microblaze. Has someone good or bad experience with the RoseRT + ThreadX + Microblaze flow? Are there any pitfalls? What kind of debugging methods ar...


Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE

Started by makhan in comp.arch.embedded12 years ago 2 replies

Hello, I am using Xilinx 9.1i and Modelsim 5.7g. I instantiated a coregen module for FFT ver 3.2. After successfully synthesizing the...

Hello, I am using Xilinx 9.1i and Modelsim 5.7g. I instantiated a coregen module for FFT ver 3.2. After successfully synthesizing the module with the generated xco, I am now trying to simulate the module. The hierarchy is as follows: fft_tb => fft_top => fft.v (generated by coregen) I am using a custom script as follows: ############################################# vlib work vlog fft


Question on Xilinx VirtexProII PCMCIA support (FPGA boards)... please

Started by Mark Levitski in comp.arch.embedded15 years ago 3 replies

I posted here before and got excellent responses, could you knowledgeable people also answer a simple questuion below? If you reply by email,...

I posted here before and got excellent responses, could you knowledgeable people also answer a simple questuion below? If you reply by email, REMOVE "SPAMNOMORE" in capital letters repeated in my address twice (edit address manually)!! We need to make sure Xilinx VirtexProII FPGA boards have a PCMCIA interface (hardware) and software support, and whether inteface is a regular one u...


DDR SDRAM with Xilinx Virtex 2 on self designed PCB

Started by Elmo in comp.arch.embedded15 years ago 3 replies

Hello, last week I started the development and design of a PCB with an FPGA (Xilinx Virtex 2) and two DDR-SDRAMs in parallel. No big deal, I...

Hello, last week I started the development and design of a PCB with an FPGA (Xilinx Virtex 2) and two DDR-SDRAMs in parallel. No big deal, I thought, keeping in mind the most obvious design rules, i.e. combining the adress lines and separating the data and strobe (DQS) lines. But now I came across the many other signals there are, e.g. the clock signals, S0 and S1, CAS, RAS, WE, etc. My fi...


Software Defined Radio on Xilinx Virtex 4

Started by augu...@googlemail.com in comp.arch.embedded12 years ago 5 replies

Hello, Let me right again in this forum on the same topic. But know in English. Whatever my English is very poor. I am working for about 4...

Hello, Let me right again in this forum on the same topic. But know in English. Whatever my English is very poor. I am working for about 4 month's ego with an ML405 Xilinx Virtex 4 board and I wanted now to implement a Software Defined Radio (SDR). I understand everything that relates to SDR (theory, operation, Etc..) Very good. Likewise, I also understand VHDL and VERILOG. Now I would li...


[Urgent help needed] How to get the messages (with display, or monitor command) in Xilinx?

Started by thexmask in comp.arch.embedded11 years ago

Hi... I'm a newbie working in Xilinx 10.1 ISE. I coded a simple program in verilog (a 2-to-1 MUX) and perform the synthesis. To show the...

Hi... I'm a newbie working in Xilinx 10.1 ISE. I coded a simple program in verilog (a 2-to-1 MUX) and perform the synthesis. To show the output I used display and monitor command. The synthesis goes on successfully, but there is no message on display. The messages are the only way to understand if the test-bench is working correct, or not. I've been searching for the view-pane for one hour...


jitter-sensitive multi-output clk distribution for multi-gigabit-transceivers

Started by Toni Merwec in comp.arch.embedded12 years ago 2 replies

Hi there, I am currently designing an FPGA board, featuring two Xilinx Virtex-4 FPGAs. I've already posted another question concerning a...

Hi there, I am currently designing an FPGA board, featuring two Xilinx Virtex-4 FPGAs. I've already posted another question concerning a correct JTAG chain implementation a few days ago and gained pretty good response. But some problems remain... although on another topic: I'll be using the Xilinx Virtex-4 FX series FPGAs featuring the high-speed MGTs. The MGTs are located in two row...


linker script help on PPC 405 on Xilinx VII pro chip

Started by sdarch in comp.arch.embedded14 years ago

I'm new to Xilinx EDK 7.1 and want to get my own simple programs to work. I have a development board from AVNET and I got their test programs...

I'm new to Xilinx EDK 7.1 and want to get my own simple programs to work. I have a development board from AVNET and I got their test programs to work (flashing LEDs ..etc.). I am using the xilkernel on a PPC 405. So next thing I do is use SDK to write a test hello world program. It seems to compile. But then when I use XMD to download it to the board I get a linker error. So then I think,...


PC/104 plus bus communication with FPGA using Xilinx IPCore

Started by awa in comp.arch.embedded13 years ago 2 replies

Hi, I was wondering if anyone has ever use FPGA to communicate with another board that use PC/104 plus bus as the interface? To give a better...

Hi, I was wondering if anyone has ever use FPGA to communicate with another board that use PC/104 plus bus as the interface? To give a better view, I have one firewire board that uses a PCI-to-1394 host chip and another board that has an FPGA on it. I would like to control the firewire by using the FPGA. Does anyone has any suggestion on how to do this? I've tried using Xilinx PCi IPCor...


How to independently program the embedded PowerPC in a Virtex?

Started by Denkedran Joe in comp.arch.embedded12 years ago 3 replies

Hi, I'm using a Xilinx Virtex-II Pro FPGA on a self-designed PCB and I'd like to ask for a way to program the embedded PowerPC independently...

Hi, I'm using a Xilinx Virtex-II Pro FPGA on a self-designed PCB and I'd like to ask for a way to program the embedded PowerPC independently from booting the whole FPGA via the Xilinx Platform Flash. Is there a way to account for that, maybe be designing an additional Flash device in the BS chain? Is it even possible to run the PowerPC even though the FPGA is not programmed? Regards ...


USB interface in Xilinx ML310 board

Started by leena in comp.arch.embedded14 years ago 2 replies

I am facing problem in interfacing USB port with xilinx ML310 board. found that on the board USB port is connected to ALi M1535 south...

I am facing problem in interfacing USB port with xilinx ML310 board. found that on the board USB port is connected to ALi M1535 south bridg through PCI bus to VIrtex II pro device. But I am not getting any clue t start accessing USB/M1535 device. please help me as soon as possible. regards leena This message was sent using the comp.arch.embedded web interface o www.EmbeddedRelate...


Board data wrong on Xilinx ML403 board

Started by Anonymous in comp.arch.embedded13 years ago

Anyone, I am trying to get linux to run on a Xlinix ML403 board. I am using an elf file to boot from. I'm using 'xmd' from Xilinx to...

Anyone, I am trying to get linux to run on a Xlinix ML403 board. I am using an elf file to boot from. I'm using 'xmd' from Xilinx to download the kernel. Once I download the kernel, I'm using the run command to start the boot process. At this point, the kernel loads and uncompresses but it doesn't boot. I get the following output: loaded at: 00400000 004FA1A0 board data at...


using the mex file model for xfft_v5 Xilinx core-generator

Started by Anonymous in comp.arch.embedded12 years ago 1 reply

Hi, Does anybody have any experience in using the mex file provided by xilinx core-generator for xfft_v5 to model the characteristics of...

Hi, Does anybody have any experience in using the mex file provided by xilinx core-generator for xfft_v5 to model the characteristics of the bit-accurate FFT FPGA core in matlab? I put the mex file in the same directory as where i am running matlab. and follow the instructions closely on how to call the mex function this is the error i get. ?? invalid mex file C:\xfft_v5_0_bitacc_...


[OT] 2 full-time openings at Xilinx (embedded systems, embedded software, SoC, FPGA)

Started by Anonymous in comp.arch.embedded6 years ago

Hello, Xilinx (San Jose, California) has 2 full-time openings for people interested in software development, embedded systems, SoC chips, ARM...

Hello, Xilinx (San Jose, California) has 2 full-time openings for people interested in software development, embedded systems, SoC chips, ARM architecture and FPGAs. Ideal candidate would love seeing hardware and software cooperate. As a member of our team you'll spend most of your time with Vim/Emacs, designing, writing, testing and breaking our proprietary OS. It's written in B