Hi All, Here is a open-source CableServer replacement for Impact. Currently Parallel III and Alter ByteBlaster are supported, but any 3rd...

Hi All, Here is a open-source CableServer replacement for Impact. Currently Parallel III and Alter ByteBlaster are supported, but any 3rd party can be implemented easily and can be used from Impact. I've tested only Impact 8.2, if anybody has any problem with 7.1, please let me know! Impact and Xilinx CableServer communication are very pooly written. There is no error recovery at all....

currently i try to write a simple interrupt driven timer example without using the provided help functions in the xilinx edk. The goal is to...

currently i try to write a simple interrupt driven timer example without using the provided help functions in the xilinx edk. The goal is to reduce the code size for a minimal system configuration. The xilinx functions blows up the code, so i try to program the timer and interrupt controller components by my self. So these works, i receive the timer interrupt. My problem is now, that the han...

I've recently upgraded a ppc405 build for a Virtex 4 device from kernel 2.6.15 (arch/ppc) to 2.6.31 (arch/powerpc) and the size of the image has...

I've recently upgraded a ppc405 build for a Virtex 4 device from kernel 2.6.15 (arch/ppc) to 2.6.31 (arch/powerpc) and the size of the image has increased from about 900k to 1.4M. As far as I can tell I've pretty much the same config options set. The 2.6.15 kernel was straight from the kernel mainline with some xilinx drivers hacked in, the .31 is straight from git.xilinx.com with nothing ...

Hi, I would like to develop software by means of RoseRT, and running it using the ThreadX OS and a Xilinx Microblaze softcore. There seems to...

Hi, I would like to develop software by means of RoseRT, and running it using the ThreadX OS and a Xilinx Microblaze softcore. There seems to be a Target Adaptation Layer for ThreadX available for RoseRT and there is a ThreadX version of Microblaze. Has someone good or bad experience with the RoseRT + ThreadX + Microblaze flow? Are there any pitfalls? What kind of debugging methods ar...

Hello, I am using Xilinx 9.1i and Modelsim 5.7g. I instantiated a coregen module for FFT ver 3.2. After successfully synthesizing the...

Hello, I am using Xilinx 9.1i and Modelsim 5.7g. I instantiated a coregen module for FFT ver 3.2. After successfully synthesizing the module with the generated xco, I am now trying to simulate the module. The hierarchy is as follows: fft_tb => fft_top => fft.v (generated by coregen) I am using a custom script as follows: ############################################# vlib work vlog fft

Hello, last week I started the development and design of a PCB with an FPGA (Xilinx Virtex 2) and two DDR-SDRAMs in parallel. No big deal, I...

Hello, last week I started the development and design of a PCB with an FPGA (Xilinx Virtex 2) and two DDR-SDRAMs in parallel. No big deal, I thought, keeping in mind the most obvious design rules, i.e. combining the adress lines and separating the data and strobe (DQS) lines. But now I came across the many other signals there are, e.g. the clock signals, S0 and S1, CAS, RAS, WE, etc. My fi...

I posted here before and got excellent responses, could you knowledgeable people also answer a simple questuion below? If you reply by email,...

I posted here before and got excellent responses, could you knowledgeable people also answer a simple questuion below? If you reply by email, REMOVE "SPAMNOMORE" in capital letters repeated in my address twice (edit address manually)!! We need to make sure Xilinx VirtexProII FPGA boards have a PCMCIA interface (hardware) and software support, and whether inteface is a regular one u...

Hello, Let me right again in this forum on the same topic. But know in English. Whatever my English is very poor. I am working for about 4...

Hello, Let me right again in this forum on the same topic. But know in English. Whatever my English is very poor. I am working for about 4 month's ego with an ML405 Xilinx Virtex 4 board and I wanted now to implement a Software Defined Radio (SDR). I understand everything that relates to SDR (theory, operation, Etc..) Very good. Likewise, I also understand VHDL and VERILOG. Now I would li...

Hi there, I am currently designing an FPGA board, featuring two Xilinx Virtex-4 FPGAs. I've already posted another question concerning a...

Hi there, I am currently designing an FPGA board, featuring two Xilinx Virtex-4 FPGAs. I've already posted another question concerning a correct JTAG chain implementation a few days ago and gained pretty good response. But some problems remain... although on another topic: I'll be using the Xilinx Virtex-4 FX series FPGAs featuring the high-speed MGTs. The MGTs are located in two row...

I'm new to Xilinx EDK 7.1 and want to get my own simple programs to work. I have a development board from AVNET and I got their test programs...

I'm new to Xilinx EDK 7.1 and want to get my own simple programs to work. I have a development board from AVNET and I got their test programs to work (flashing LEDs ..etc.). I am using the xilkernel on a PPC 405. So next thing I do is use SDK to write a test hello world program. It seems to compile. But then when I use XMD to download it to the board I get a linker error. So then I think,...

Hi, I was wondering if anyone has ever use FPGA to communicate with another board that use PC/104 plus bus as the interface? To give a better...

Hi, I was wondering if anyone has ever use FPGA to communicate with another board that use PC/104 plus bus as the interface? To give a better view, I have one firewire board that uses a PCI-to-1394 host chip and another board that has an FPGA on it. I would like to control the firewire by using the FPGA. Does anyone has any suggestion on how to do this? I've tried using Xilinx PCi IPCor...

Hi, I'm using a Xilinx Virtex-II Pro FPGA on a self-designed PCB and I'd like to ask for a way to program the embedded PowerPC independently...

Hi, I'm using a Xilinx Virtex-II Pro FPGA on a self-designed PCB and I'd like to ask for a way to program the embedded PowerPC independently from booting the whole FPGA via the Xilinx Platform Flash. Is there a way to account for that, maybe be designing an additional Flash device in the BS chain? Is it even possible to run the PowerPC even though the FPGA is not programmed? Regards ...

I am facing problem in interfacing USB port with xilinx ML310 board. found that on the board USB port is connected to ALi M1535 south...

I am facing problem in interfacing USB port with xilinx ML310 board. found that on the board USB port is connected to ALi M1535 south bridg through PCI bus to VIrtex II pro device. But I am not getting any clue t start accessing USB/M1535 device. please help me as soon as possible. regards leena This message was sent using the comp.arch.embedded web interface o www.EmbeddedRelate...

Hi, Does anybody have any experience in using the mex file provided by xilinx core-generator for xfft_v5 to model the characteristics of...

Hi, Does anybody have any experience in using the mex file provided by xilinx core-generator for xfft_v5 to model the characteristics of the bit-accurate FFT FPGA core in matlab? I put the mex file in the same directory as where i am running matlab. and follow the instructions closely on how to call the mex function this is the error i get. ?? invalid mex file C:\xfft_v5_0_bitacc_...

Hello, Xilinx (San Jose, California) has 2 full-time openings for people interested in software development, embedded systems, SoC chips, ARM...

Hello, Xilinx (San Jose, California) has 2 full-time openings for people interested in software development, embedded systems, SoC chips, ARM architecture and FPGAs. Ideal candidate would love seeing hardware and software cooperate. As a member of our team you'll spend most of your time with Vim/Emacs, designing, writing, testing and breaking our proprietary OS. It's written in B

Hi, I have faced a problem with communication via Ethernet switch Marvell 88E6320 connected to the Xilinx ZynqMP chip via RGMII...

Hi, I have faced a problem with communication via Ethernet switch Marvell 88E6320 connected to the Xilinx ZynqMP chip via RGMII interface. The whole problem and its resolution is described here: https://forums.xilinx.com/t5/Embedded-Linux/Problem-with-Marvell-88E6320-connected-to-GEM3-in-Zy nqMP/m-p/904302/highlight/false#M29845 The solution simply applies to 88E6320 chip the method t

Hi everyone, I'm working on a conversion project where we needed to convert a PCI acquisition card to a PCI-express (x1) acquisition card. The...

Hi everyone, I'm working on a conversion project where we needed to convert a PCI acquisition card to a PCI-express (x1) acquisition card. The project is essentially the same except instead that the new acquisition card is a PCI-express endpoint instead of being a standard-PCI endpoint. The project is implemented on a Xilinx FPGA, but I don't think my issue is Xilinx specific. The conve...

Hi, I need a PCI parallel port card since the new PC is "legacy free". I use parallel port based JTAG debuggers and programmers for...

Hi, I need a PCI parallel port card since the new PC is "legacy free". I use parallel port based JTAG debuggers and programmers for micros (AVRs), CPLDs (Xilinx/Altera/Lattice) and FPGAs (Xilinx/Altera). Which PCI parallel cards work or don't work for you? Tried it under Linux? Seems like most PCI parallel cards are based on chipsets from Netmos -- any luck with these? Thanks.

Hi, I am newbie in FPGA field. I am trying to implement look up table based logic on Xilinx FPGA. I want to implement the look up table in ...

Hi, I am newbie in FPGA field. I am trying to implement look up table based logic on Xilinx FPGA. I want to implement the look up table in distributed RAM and to connect the output of RAM to implement the logic in LUT. And to get reconfigurability modify the RAM content at run time by soft core processor on the same chip. Can anybody let me know if it is feasible or not. Thanks, Indra ...

Hallo, ich arbeite seit 3 Monaten mit einem Xilinx Ml405 Virtex 4 Board und wollte darauf nun mal ein Software Defined Radio...

Hallo, ich arbeite seit 3 Monaten mit einem Xilinx Ml405 Virtex 4 Board und wollte darauf nun mal ein Software Defined Radio (SDR) implementieren. Ich verstehe alles was auf SDR betrifft (Theorie, Funktionsweise, etc..) ganz gut . Genauso kann ich auch VHDL und VERILOG. Jetzt w=FCrde ich gerne wissen, ob Jemand sich damit auch besch=E4ftigt einem SDR auf oben genanntem Board (oder anderen...