Embedded Linux - Delay control implemented for Marvell 88E6352/1 also works for 88E6320

Started by Wojciech M. Zabolotny in comp.arch.embedded1 year ago

Hi, I have faced a problem with communication via Ethernet switch Marvell 88E6320 connected to the Xilinx ZynqMP chip via RGMII...

Hi, I have faced a problem with communication via Ethernet switch Marvell 88E6320 connected to the Xilinx ZynqMP chip via RGMII interface. The whole problem and its resolution is described here: https://forums.xilinx.com/t5/Embedded-Linux/Problem-with-Marvell-88E6320-connected-to-GEM3-in-Zy nqMP/m-p/904302/highlight/false#M29845 The solution simply applies to 88E6320 chip the method t


Question on PCI-express verssus Standard PCI performance

Started by Benjamin Couillard in comp.arch.embedded9 years ago 6 replies

Hi everyone, I'm working on a conversion project where we needed to convert a PCI acquisition card to a PCI-express (x1) acquisition card. The...

Hi everyone, I'm working on a conversion project where we needed to convert a PCI acquisition card to a PCI-express (x1) acquisition card. The project is essentially the same except instead that the new acquisition card is a PCI-express endpoint instead of being a standard-PCI endpoint. The project is implemented on a Xilinx FPGA, but I don't think my issue is Xilinx specific. The conve...


PCI Parallel port card for JTAG / programming?

Started by ee_ether in comp.arch.embedded12 years ago 5 replies

Hi, I need a PCI parallel port card since the new PC is "legacy free". I use parallel port based JTAG debuggers and programmers for...

Hi, I need a PCI parallel port card since the new PC is "legacy free". I use parallel port based JTAG debuggers and programmers for micros (AVRs), CPLDs (Xilinx/Altera/Lattice) and FPGAs (Xilinx/Altera). Which PCI parallel cards work or don't work for you? Tried it under Linux? Seems like most PCI parallel cards are based on chipsets from Netmos -- any luck with these? Thanks.


Can distributed RAM on Xilinx FPGA be modified by onchip processor at run time and can output of the same connected to shift register in CLB.

Started by iwgauba in comp.arch.embedded11 years ago 1 reply

Hi, I am newbie in FPGA field. I am trying to implement look up table based logic on Xilinx FPGA. I want to implement the look up table in ...

Hi, I am newbie in FPGA field. I am trying to implement look up table based logic on Xilinx FPGA. I want to implement the look up table in distributed RAM and to connect the output of RAM to implement the logic in LUT. And to get reconfigurability modify the RAM content at run time by soft core processor on the same chip. Can anybody let me know if it is feasible or not. Thanks, Indra ...


Software Defined Radio auf Xilinx Virtex 4

Started by Anonymous in comp.arch.embedded12 years ago 3 replies

Hallo, ich arbeite seit 3 Monaten mit einem Xilinx Ml405 Virtex 4 Board und wollte darauf nun mal ein Software Defined Radio...

Hallo, ich arbeite seit 3 Monaten mit einem Xilinx Ml405 Virtex 4 Board und wollte darauf nun mal ein Software Defined Radio (SDR) implementieren. Ich verstehe alles was auf SDR betrifft (Theorie, Funktionsweise, etc..) ganz gut . Genauso kann ich auch VHDL und VERILOG. Jetzt w=FCrde ich gerne wissen, ob Jemand sich damit auch besch=E4ftigt einem SDR auf oben genanntem Board (oder anderen...


what does a 'blank check' do exactly

Started by Anonymous in comp.arch.embedded13 years ago 14 replies

on lets say... a Xilinx CoolRunner 2 CPLD? I had trouble finding information on this. Using Impact. thanks!

on lets say... a Xilinx CoolRunner 2 CPLD? I had trouble finding information on this. Using Impact. thanks!


Xilinx: XC3030

Started by Val in comp.arch.embedded15 years ago 2 replies

Hi All, What software do I need to create a load for XC3030? Thanks Val

Hi All, What software do I need to create a load for XC3030? Thanks Val


Address decoder problem

Started by Fizzy in comp.arch.embedded14 years ago 5 replies

Can anyone translate following for me. I found this as a default value into one of the slice blocks in system generator for xilinx FPGA....

Can anyone translate following for me. I found this as a default value into one of the slice blocks in system generator for xilinx FPGA. This block actually decode the address from the bus 32-ceil(log2(C_HIGH-C_BASE))


No way to program a Spartan 3 FPGA with a1,8V Digilent cable?

Started by blisca in comp.arch.embedded12 years ago 2 replies

I have a t home some "accurately scraped " FPGA Xilinx XC3S1500,having a VCCINT of 1,2 V, no way to use a cable rated 1,8 to 15 V to configure...

I have a t home some "accurately scraped " FPGA Xilinx XC3S1500,having a VCCINT of 1,2 V, no way to use a cable rated 1,8 to 15 V to configure it? Thanks, Diego,Italy


Virtex 2 Pro and PPC405

Started by Anonymous in comp.arch.embedded15 years ago 2 replies

I have been looking around for a while. I dont want to use the EDK from Xilinx. Is there any free c compiler for ppc405 processor. I found...

I have been looking around for a while. I dont want to use the EDK from Xilinx. Is there any free c compiler for ppc405 processor. I found gcc, but did not find any binary distro or any auto-compile script.. Would be great if it could run from win32 or linux. - Thomas


Availability of CPLDs

Started by Fred in comp.arch.embedded16 years ago 9 replies

At present I am concerned over the lead time of CPLDs. Both Altera and Xilinx have had, in the past, very embarrassing lead times which would...

At present I am concerned over the lead time of CPLDs. Both Altera and Xilinx have had, in the past, very embarrassing lead times which would be unacceptable in a product I am about to design. Can anyone give an indication of their experiences?


Gigabit Ethernet

Started by josesmn in comp.arch.embedded11 years ago 1 reply

Does any body know any Xilinx Fpgas with in built PHY of Gigabit Ethernet? Please let me know!!!

Does any body know any Xilinx Fpgas with in built PHY of Gigabit Ethernet? Please let me know!!!


problem regarding SDK for PowerPC

Started by neeraj in comp.arch.embedded14 years ago 1 reply

Hello, I am using Xilinx Platform Studio SDK ,Release Version: 8.1.0. I have doubt that, Is it possible to debug and simulate...

Hello, I am using Xilinx Platform Studio SDK ,Release Version: 8.1.0. I have doubt that, Is it possible to debug and simulate software application through SDK without connecting hardware board to it. if any body have answer to it please reply to ss2neeraj@gmail.com


Parallel Cable IV

Started by mazamshahid in comp.arch.embedded11 years ago 3 replies

Dear All, I am working on Xilinx EDk and microblaze. I am facing some problems while downloading my .bit file onto FPGA. Sometimes FPGA is...

Dear All, I am working on Xilinx EDk and microblaze. I am facing some problems while downloading my .bit file onto FPGA. Sometimes FPGA is programmed successfully and sometimes it fails. Are some other people facing such problem? What might be the possible reasons? Somebody please advise me... Azam


MPC5200 boundary scan problems

Started by Didi in comp.arch.embedded13 years ago 3 replies

Hi everyone, I am setting up my tools for an MPC5200 based device I have designed. I have been using these tools (which like all...

Hi everyone, I am setting up my tools for an MPC5200 based device I have designed. I have been using these tools (which like all development software here, are my doing) on the MPC8240, on the MC68340, and some others (TI, Xilinx parts) but now the 5200 seems to be more stubborn than they usually are. The problem I am stuck with since yesterday is the fact that I cannot preload the bound...


FPGA Internals

Started by prasadbgm in comp.arch.embedded15 years ago 1 reply

Hi, Can anybody suggest me some good reading regarding the FPGA architecture Internals of FPGA. What is the Difference between Xilinx "Logic...

Hi, Can anybody suggest me some good reading regarding the FPGA architecture Internals of FPGA. What is the Difference between Xilinx "Logic gates" & Altera's "Logi Elements". Thank you This message was sent using the comp.arch.embedded web interface o www.EmbeddedRelated.com


V4 and NBTI question (again)

Started by Antti Lukats in comp.arch.embedded15 years ago 1 reply

Hi Xilinx answer record 21127 and related information, - I am still a little unsure if I did understood it all correctly and what the actual...

Hi Xilinx answer record 21127 and related information, - I am still a little unsure if I did understood it all correctly and what the actual impact of the NBTI issues actually are. I have had some trouble with DCM lately, so I am little bit more worried, AR21127 says that if the V4 is powered but not configured the DCM performance will start to degrade (there are actuall changes of the ...


XiliKernel

Started by Fizzy in comp.arch.embedded14 years ago 1 reply

HI, Any of you have used XilKernel in application for PowerPC 405. I am required to develop a system based on embedded PowerPC 405 on...

HI, Any of you have used XilKernel in application for PowerPC 405. I am required to develop a system based on embedded PowerPC 405 on Xilinx Virtex4 FPGA. Since i have 4 processes running on the uP so i want to schedule them in round robin fashion. Just wondering if any one can tell me how hard it is to do. I cannot use any other OS since this kernel is free and as document said very compa...


Interfacing LAN91C111 with spartan 3 using EPC

Started by ratemonotonic in comp.arch.embedded12 years ago 2 replies

Hi all , I am about to start a designing a system using Spartan 3 FPGA running microblaze and interface it with SMSC LAN91C111 using the...

Hi all , I am about to start a designing a system using Spartan 3 FPGA running microblaze and interface it with SMSC LAN91C111 using the Embedded peripheral controller core provided by xilinx. Just before starting I thought it worth checking if some one had any problems using such a setup ? BR Rate


Microblaze, EDK, Spartan 3 and Webpack

Started by larwe in comp.arch.embedded14 years ago 13 replies

I'm drowning in Xilinx documentation and downloads. I have the ML403, which includes a Base-X version of ISE, and uBlaze IP. Is that core only...

I'm drowning in Xilinx documentation and downloads. I have the ML403, which includes a Base-X version of ISE, and uBlaze IP. Is that core only licensed for use in Virtex-4 designs, or is it permissible to use it in a Spartan 3 also? The reason I ask this is because I just found out how much the Virtex 4 FX chip costs by itself, and I'm thinking I probably ought to follow the advice I got...