Interfacing Spartan-3 to PC

Started by vekos in comp.arch.embedded11 years ago 1 reply

Hi, I have the Xilinx spartan-3 development kit and I am tying to connect it to PC troughs Ethernet connection. On the board there is a...

Hi, I have the Xilinx spartan-3 development kit and I am tying to connect it to PC troughs Ethernet connection. On the board there is a physical layer transceiver (DP83847). My data is stored in a FIFO memory inside of the FPGA. I would like to transmit it to the PC. Can someone suggest me how can I do that? I understood that I have to implement IP core on the FPGA and what else...? Thanks ...


Xilinx XC4VLX40-10FFG1148C - Available New

Started by Anonymous in comp.arch.embedded4 years ago

I recently aquired 9 quantities of XC4VLX40-10FFG1148C from a company. The ICs are in original sealed envelope (not opened). Reference:...

I recently aquired 9 quantities of XC4VLX40-10FFG1148C from a company. The ICs are in original sealed envelope (not opened). Reference: http://www.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=122-1491-ND Please let me know whether anyone will by interested to buy this from me. Thanks Mahendra Varman


Xilinx XC4VLX40-10FFG1148C - Available New

Started by Anonymous in comp.arch.embedded13 years ago

I recently aquired 9 quantities of XC4VLX40-10FFG1148C from a company. The ICs are in original sealed envelope (not opened). Reference:...

I recently aquired 9 quantities of XC4VLX40-10FFG1148C from a company. The ICs are in original sealed envelope (not opened). Reference: http://www.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=122-1491-ND Please let me know whether anyone will by interested to buy this from me. Thanks Mahendra Varman


FIFO hdl code

Started by Anonymous in comp.arch.embedded15 years ago 4 replies

Hi, I need to stream audio data and control info I2C out of my PC into some external hardware and was thinking of using a FIFO to deal with the...

Hi, I need to stream audio data and control info I2C out of my PC into some external hardware and was thinking of using a FIFO to deal with the different clock boundaries. I was wondering if anyone had some startup verilog code on FIFOs, I am using a Xilinx FPGA Thanks Ryan (ryan.pinto79@gmail.com)


Bitstream programming

Started by quad in comp.arch.embedded13 years ago 2 replies

Hello I've started working on Xilinx Virtex II PRo FPGA kit for a project. Is there a way to configure bitstreams or netlists programmatically...

Hello I've started working on Xilinx Virtex II PRo FPGA kit for a project. Is there a way to configure bitstreams or netlists programmatically using C (i'm not looking at JBits!) so that i can configure the LUTs,IOBs according to my circuit needs? I also need to invoke iMPACT several times in my code to evaluate the fitness of my circuit. Will OLE automation be a solution to this problem? ...


Xilinx Virtex5 ILOGIC LOCations

Started by SCO in comp.arch.embedded12 years ago

Hi, I have generated a DDR2 SDRAM interface with MIG2.0. It gave me a nice project but I have to change the pin locations. After I make...

Hi, I have generated a DDR2 SDRAM interface with MIG2.0. It gave me a nice project but I have to change the pin locations. After I make the necessary changes I see that I have to tweak the ILOGIC, IODELAY element locations also. They have location names like ---------------------------------------------------------------------- INST "*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y30...


PPC405 sleep?

Started by Bo in comp.arch.embedded15 years ago 6 replies

I am trying to put the PPC405 asleep on a VirtexIIPro ML310 Xilinx development board and not have a lot of luck. I'm running VxWorks and have...

I am trying to put the PPC405 asleep on a VirtexIIPro ML310 Xilinx development board and not have a lot of luck. I'm running VxWorks and have written a little application that toggles an LED so that I know the task is running. I've tried two methods--with drastically different results-- but neither of which do everything I need. First try: I loaded my app that toggles LEDs via a Tor...


CPLD and FPGA designs

Started by Scott McDonnell in comp.arch.embedded16 years ago 11 replies

Ok, I am about to get myself a dev kit from Xilinx or Lattice to start working in HDL language. The know the basics of HDL programming, and...

Ok, I am about to get myself a dev kit from Xilinx or Lattice to start working in HDL language. The know the basics of HDL programming, and have the materials to learn the rest, now I just need to start experimenting with real parts. This question is about synthesis (and is a bit premature, I confess.) The only disadvantage I see to using FPGAs in a design is that some kind of ROM must be ...


lwip for FPGA

Started by Anonymous in comp.arch.embedded12 years ago 3 replies

Hi, I am new to using lwip. I am wondering if you can advice me on the same. I need to transfer data from PC to Microblaze microprocessor...

Hi, I am new to using lwip. I am wondering if you can advice me on the same. I need to transfer data from PC to Microblaze microprocessor on a Xilinx FPGA board and vice versa as fast as possible. i dun need any error correction or the overheads like full TCP/IP. I am currently readin this article to understand about socket programming as an initial start: http://cscene.unitycode.o...


C8051F022 and FPGA communication

Started by methi in comp.arch.embedded15 years ago 1 reply

Hi, I am currently working on Cygnal's C8051F022....I need this to communicate with a Xilinx FPGA on the board....I am using Port 0 for talking...

Hi, I am currently working on Cygnal's C8051F022....I need this to communicate with a Xilinx FPGA on the board....I am using Port 0 for talking to the FPGA.....What i need to do is..as follows: I have an 8 charactor display and two momentary contact switches... One switch is for selecting menu and another is for entering tat value The microcontroller takes care of the two switches and the ...


How To Synchronize FPGAs

Started by Leroy Tanner in comp.arch.embedded15 years ago 10 replies

Hello newsreaders, For a while I have been confronted with the following task which I find quite challenging but unfortuantely didn't manage...

Hello newsreaders, For a while I have been confronted with the following task which I find quite challenging but unfortuantely didn't manage to solve it, yet. What I want to do is to use 2-4 FPGAs (Xilinx Virtex 2 Pro) together on one printed circuit board (PCB). They are used to process a large amount of incoming serial data (data rates of several GHz's). My idea is to handle that data pa...


embedded linux on FPGA?

Started by hol in comp.arch.embedded15 years ago 19 replies

One of our customers will be asking us to implement a bunch of math functions on an FPGA-boards. There are a lot of "decisions" that affect...

One of our customers will be asking us to implement a bunch of math functions on an FPGA-boards. There are a lot of "decisions" that affect control processing/algorithm selection, so they specifically requested an FPGA with "PowerPC." (This immediately tells me Xilinx's marketing has done an A+ job of getting managers and other non-technical people to subconsciously associate 'FPGA CPU' wi...


NGDBuild error and NCD not produced

Started by quad in comp.arch.embedded13 years ago

Hello I'm working on Xilinx virtex II Pro FPGA kit.I generated netlist for OR gate using JHDL, with a1 and a2 being inputs, and op being...

Hello I'm working on Xilinx virtex II Pro FPGA kit.I generated netlist for OR gate using JHDL, with a1 and a2 being inputs, and op being the output. I also created the following User constraint file: (not sure if the given constraints are right!) NET "a1" LOC="AC4"; NET "a2" LOC="AC3"; NET "op" LOC="AA6"; ...


Linux on Microblaze

Started by m in comp.arch.embedded11 years ago 15 replies

I'm interested to hear from anyone who has experience implementing Linux on Microblaze. How "smooth" is it? What are the...

I'm interested to hear from anyone who has experience implementing Linux on Microblaze. How "smooth" is it? What are the pitfalls? Limitations/issues? I am not talking about uClinux but rather the MMU version/s. I hear conflicting reports. Hard processor vendors bash the heck out of it and tell us that it is an absolute nightmare (gee, I wonder why?). Xilinx and the disti are telling...


Xilinx PPC unexplainable cycle count

Started by Anonymous in comp.arch.embedded14 years ago 1 reply

Hello, This is what I am experiencing: - I need to compare to code versions regarding execution speed - comparison is done counting cycles,...

Hello, This is what I am experiencing: - I need to compare to code versions regarding execution speed - comparison is done counting cycles, using the time base registers - the only difference in code is the following: #if POST_PROC_CS_UPD // do nothing #else update_checksum(); #endif When compiled with POST_PROC_CS_UPD = 1 the execution time of this portion i...


Help installing proc_common_v3_00_a

Started by Anonymous in comp.arch.embedded11 years ago

Hello, One of my peripherals is using proc_common_v3_00_a library, while the rest proc_common_v2_0*. Is it safe to add both libraries to...

Hello, One of my peripherals is using proc_common_v3_00_a library, while the rest proc_common_v2_0*. Is it safe to add both libraries to the project and let peripherals use the ones they need? Also, how could I add proc_common_v3_00_a if I have only access to my local project folder (and not Xilinx installation)? Thank you in advance


about uclinux network setting???

Started by in comp.arch.embedded12 years ago 3 replies

i have a question. i implement uclinux on xilinx ml403.i turn on promiscouse mode, but i only receive brocast packet,not promiscouse mode...

i have a question. i implement uclinux on xilinx ml403.i turn on promiscouse mode, but i only receive brocast packet,not promiscouse mode packet, what's happen ? what's next step i will be do??? on uclinux kernel or ethernet driver???


xilinx microblaze and picoblaze on a spartan 3e starter kit

Started by llombard in comp.arch.embedded12 years ago 3 replies

Dear all, I'm trying to make an IP for microblaze using code including a Picoblaze processor. So that's a pico/micro blaze mix on a spartan...

Dear all, I'm trying to make an IP for microblaze using code including a Picoblaze processor. So that's a pico/micro blaze mix on a spartan 3e and it seems to be incompatible because of BSCANS: Number of BSCANs: 2 out of 1 200% (OVERMAPPED) Does anyone has a clue on how to solve that? thanks in advance, Laurent


Soft ARM in an FPGA

Started by arm_newbie in comp.arch.embedded11 years ago 6 replies

Sorry if this is a repeat post. . . I'm trying to understand the reasons why someone would put a soft ARM processor in an FPGA. Both Xilinx and...

Sorry if this is a repeat post. . . I'm trying to understand the reasons why someone would put a soft ARM processor in an FPGA. Both Xilinx and Altera have fine 32-bit offerings that have good development environments, growing ecosystems, and rich catalogs of IP. I suspect it has something to do with ARM being an industry standard or something like that, but the reality is that the ARM will...


Production Programming of Flash for FPGAs and MCUs

Started by rickman in comp.arch.embedded8 years ago 15 replies

Someone on Linkedin asked about a stand alone device for programming the flash for FPGAs in the field or in a production environment. There...

Someone on Linkedin asked about a stand alone device for programming the flash for FPGAs in the field or in a production environment. There doesn't seem to be anything currently available like this. Looking at the big three manufacturers I see at least two formats for the files that might be used. Xilinx and Lattice use SVF with Xilins offering support for a compressed version called... XSVF...