I am trying to put the PPC405 asleep on a VirtexIIPro ML310 Xilinx development board and not have a lot of luck. I'm running VxWorks and have...

I am trying to put the PPC405 asleep on a VirtexIIPro ML310 Xilinx development board and not have a lot of luck. I'm running VxWorks and have written a little application that toggles an LED so that I know the task is running. I've tried two methods--with drastically different results-- but neither of which do everything I need. First try: I loaded my app that toggles LEDs via a Tor...

Ok, I am about to get myself a dev kit from Xilinx or Lattice to start working in HDL language. The know the basics of HDL programming, and...

Ok, I am about to get myself a dev kit from Xilinx or Lattice to start working in HDL language. The know the basics of HDL programming, and have the materials to learn the rest, now I just need to start experimenting with real parts. This question is about synthesis (and is a bit premature, I confess.) The only disadvantage I see to using FPGAs in a design is that some kind of ROM must be ...

Hi, I am new to using lwip. I am wondering if you can advice me on the same. I need to transfer data from PC to Microblaze microprocessor...

Hi, I am new to using lwip. I am wondering if you can advice me on the same. I need to transfer data from PC to Microblaze microprocessor on a Xilinx FPGA board and vice versa as fast as possible. i dun need any error correction or the overheads like full TCP/IP. I am currently readin this article to understand about socket programming as an initial start: http://cscene.unitycode.o...

Hi, I am currently working on Cygnal's C8051F022....I need this to communicate with a Xilinx FPGA on the board....I am using Port 0 for talking...

Hi, I am currently working on Cygnal's C8051F022....I need this to communicate with a Xilinx FPGA on the board....I am using Port 0 for talking to the FPGA.....What i need to do is..as follows: I have an 8 charactor display and two momentary contact switches... One switch is for selecting menu and another is for entering tat value The microcontroller takes care of the two switches and the ...

Hello newsreaders, For a while I have been confronted with the following task which I find quite challenging but unfortuantely didn't manage...

Hello newsreaders, For a while I have been confronted with the following task which I find quite challenging but unfortuantely didn't manage to solve it, yet. What I want to do is to use 2-4 FPGAs (Xilinx Virtex 2 Pro) together on one printed circuit board (PCB). They are used to process a large amount of incoming serial data (data rates of several GHz's). My idea is to handle that data pa...

One of our customers will be asking us to implement a bunch of math functions on an FPGA-boards. There are a lot of "decisions" that affect...

One of our customers will be asking us to implement a bunch of math functions on an FPGA-boards. There are a lot of "decisions" that affect control processing/algorithm selection, so they specifically requested an FPGA with "PowerPC." (This immediately tells me Xilinx's marketing has done an A+ job of getting managers and other non-technical people to subconsciously associate 'FPGA CPU' wi...

Hello I'm working on Xilinx virtex II Pro FPGA kit.I generated netlist for OR gate using JHDL, with a1 and a2 being inputs, and op being...

Hello I'm working on Xilinx virtex II Pro FPGA kit.I generated netlist for OR gate using JHDL, with a1 and a2 being inputs, and op being the output. I also created the following User constraint file: (not sure if the given constraints are right!) NET "a1" LOC="AC4"; NET "a2" LOC="AC3"; NET "op" LOC="AA6"; ...

I'm interested to hear from anyone who has experience implementing Linux on Microblaze. How "smooth" is it? What are the...

I'm interested to hear from anyone who has experience implementing Linux on Microblaze. How "smooth" is it? What are the pitfalls? Limitations/issues? I am not talking about uClinux but rather the MMU version/s. I hear conflicting reports. Hard processor vendors bash the heck out of it and tell us that it is an absolute nightmare (gee, I wonder why?). Xilinx and the disti are telling...

Hello, This is what I am experiencing: - I need to compare to code versions regarding execution speed - comparison is done counting cycles,...

Hello, This is what I am experiencing: - I need to compare to code versions regarding execution speed - comparison is done counting cycles, using the time base registers - the only difference in code is the following: #if POST_PROC_CS_UPD // do nothing #else update_checksum(); #endif When compiled with POST_PROC_CS_UPD = 1 the execution time of this portion i...

Hello, One of my peripherals is using proc_common_v3_00_a library, while the rest proc_common_v2_0*. Is it safe to add both libraries to...

Hello, One of my peripherals is using proc_common_v3_00_a library, while the rest proc_common_v2_0*. Is it safe to add both libraries to the project and let peripherals use the ones they need? Also, how could I add proc_common_v3_00_a if I have only access to my local project folder (and not Xilinx installation)? Thank you in advance

i have a question. i implement uclinux on xilinx ml403.i turn on promiscouse mode, but i only receive brocast packet,not promiscouse mode...

i have a question. i implement uclinux on xilinx ml403.i turn on promiscouse mode, but i only receive brocast packet,not promiscouse mode packet, what's happen ? what's next step i will be do??? on uclinux kernel or ethernet driver???

Dear all, I'm trying to make an IP for microblaze using code including a Picoblaze processor. So that's a pico/micro blaze mix on a spartan...

Dear all, I'm trying to make an IP for microblaze using code including a Picoblaze processor. So that's a pico/micro blaze mix on a spartan 3e and it seems to be incompatible because of BSCANS: Number of BSCANs: 2 out of 1 200% (OVERMAPPED) Does anyone has a clue on how to solve that? thanks in advance, Laurent

Sorry if this is a repeat post. . . I'm trying to understand the reasons why someone would put a soft ARM processor in an FPGA. Both Xilinx and...

Sorry if this is a repeat post. . . I'm trying to understand the reasons why someone would put a soft ARM processor in an FPGA. Both Xilinx and Altera have fine 32-bit offerings that have good development environments, growing ecosystems, and rich catalogs of IP. I suspect it has something to do with ARM being an industry standard or something like that, but the reality is that the ARM will...

Someone on Linkedin asked about a stand alone device for programming the flash for FPGAs in the field or in a production environment. There...

Someone on Linkedin asked about a stand alone device for programming the flash for FPGAs in the field or in a production environment. There doesn't seem to be anything currently available like this. Looking at the big three manufacturers I see at least two formats for the files that might be used. Xilinx and Lattice use SVF with Xilins offering support for a compressed version called... XSVF...

Some time ago I managed to get (under NDA) the programming info from Xilinx so now I can program one of their coolrunners via JTAG with...

Some time ago I managed to get (under NDA) the programming info from Xilinx so now I can program one of their coolrunners via JTAG with my toolchain (the CPLD on this design is reprogrammable over the net, i.e. the board CPU does its JTAG access etc.). I am now getting to what should be the easy part - writing the CPLD source to produce some (very simple) logic in a jedec file, after wh...

Hi all , I am devoloping software fro microblaze using XPS and I dont have enough resources for a watchdog timer. I want to reset the FPGA...

Hi all , I am devoloping software fro microblaze using XPS and I dont have enough resources for a watchdog timer. I want to reset the FPGA after n number of error conditions have occured in software. Whats the most reliable way to reboot the Xilinx Spartan 3 FPGA? Any help will e much appreciated. BR Rate

Hi everybody Sorry for the basic question. I'm starting with FPGA and I'm using a Spartan-3 Starter Kit board. I would like to be able to...

Hi everybody Sorry for the basic question. I'm starting with FPGA and I'm using a Spartan-3 Starter Kit board. I would like to be able to implement a design using microblaze, let's say one of xilinx's microblaze reference designs, in a way that it runs at power-on. Do you know of a documentation that explains how to do that Tanks jmariano

hi when i work with xilinx edk (ver 8.1),after downloading my code to the V2Pro,the info below appears.but at first it is ok,and after some...

hi when i work with xilinx edk (ver 8.1),after downloading my code to the V2Pro,the info below appears.but at first it is ok,and after some times,it appears. what what should i do to solve the prolbem? "unable to connect to PowerPc target, Invalid Processor Version No 0x00000000".

Hi,all.I am doing a project which will implement SAS with FPGAs on Xilinx Virtex 4 ML405 board. But before I am a software designer and never do...

Hi,all.I am doing a project which will implement SAS with FPGAs on Xilinx Virtex 4 ML405 board. But before I am a software designer and never do IC design before ,so this project is very difficult for me.Who could help me and give me some guidances or some datum and paper about how to implement SAS with FPGAs.I will be very grateful.Thanks very much.

Hi all, i'm first time approch with fpga, i have xilinx ise and edk 6.3i version. With XPS I have create a new project with project builder...

Hi all, i'm first time approch with fpga, i have xilinx ise and edk 6.3i version. With XPS I have create a new project with project builder on spartan 3 starter development kit. When i go to compile the project the programm given back this error: Performing System level DRCs on properties... INFO:MDT - List of peripherals addressable from processor instance microblaze_0 : - dl...