XPLA3 coolrunner programming tool?

Started by Didi in comp.arch.embedded10 years ago 17 replies

Some time ago I managed to get (under NDA) the programming info from Xilinx so now I can program one of their coolrunners via JTAG with...

Some time ago I managed to get (under NDA) the programming info from Xilinx so now I can program one of their coolrunners via JTAG with my toolchain (the CPLD on this design is reprogrammable over the net, i.e. the board CPU does its JTAG access etc.). I am now getting to what should be the easy part - writing the CPLD source to produce some (very simple) logic in a jedec file, after wh...


Resetting FPGA without Watchdog timer.

Started by ratemonotonic in comp.arch.embedded12 years ago 1 reply

Hi all , I am devoloping software fro microblaze using XPS and I dont have enough resources for a watchdog timer. I want to reset the FPGA...

Hi all , I am devoloping software fro microblaze using XPS and I dont have enough resources for a watchdog timer. I want to reset the FPGA after n number of error conditions have occured in software. Whats the most reliable way to reboot the Xilinx Spartan 3 FPGA? Any help will e much appreciated. BR Rate


spartan-3 starter kit board

Started by jmariano in comp.arch.embedded14 years ago 2 replies

Hi everybody Sorry for the basic question. I'm starting with FPGA and I'm using a Spartan-3 Starter Kit board. I would like to be able to...

Hi everybody Sorry for the basic question. I'm starting with FPGA and I'm using a Spartan-3 Starter Kit board. I would like to be able to implement a design using microblaze, let's say one of xilinx's microblaze reference designs, in a way that it runs at power-on. Do you know of a documentation that explains how to do that Tanks jmariano


unable to connect to PowerPc target

Started by xtmtd in comp.arch.embedded13 years ago 1 reply

hi when i work with xilinx edk (ver 8.1),after downloading my code to the V2Pro,the info below appears.but at first it is ok,and after some...

hi when i work with xilinx edk (ver 8.1),after downloading my code to the V2Pro,the info below appears.but at first it is ok,and after some times,it appears. what what should i do to solve the prolbem? "unable to connect to PowerPc target, Invalid Processor Version No 0x00000000".


[help]SAS with FPGAs

Started by Anonymous in comp.arch.embedded12 years ago 3 replies

Hi,all.I am doing a project which will implement SAS with FPGAs on Xilinx Virtex 4 ML405 board. But before I am a software designer and never do...

Hi,all.I am doing a project which will implement SAS with FPGAs on Xilinx Virtex 4 ML405 board. But before I am a software designer and never do IC design before ,so this project is very difficult for me.Who could help me and give me some guidances or some datum and paper about how to implement SAS with FPGAs.I will be very grateful.Thanks very much.


Soft ARM in an FPGA

Started by arm_newbie in comp.arch.embedded11 years ago

I'm trying to understand what the advantage of putting a soft implementation of an ARM in an FPGA (Altera or Xilinx) is. The reason I ask is both...

I'm trying to understand what the advantage of putting a soft implementation of an ARM in an FPGA (Altera or Xilinx) is. The reason I ask is both of them have entirely adequate 32-bit soft processors of their own. Each has a nice development environment with lots of IP, growing ecosystems, and will run easily 3x to 4x the clock speed of the soft ARM. I suspect it has something to do with "indus...


problem with edk 6.3i

Started by R!SC in comp.arch.embedded15 years ago 2 replies

Hi all, i'm first time approch with fpga, i have xilinx ise and edk 6.3i version. With XPS I have create a new project with project builder...

Hi all, i'm first time approch with fpga, i have xilinx ise and edk 6.3i version. With XPS I have create a new project with project builder on spartan 3 starter development kit. When i go to compile the project the programm given back this error: Performing System level DRCs on properties... INFO:MDT - List of peripherals addressable from processor instance microblaze_0 : - dl...


Partial reconfiguration using ICAP

Started by ajit...@gmail.com in comp.arch.embedded12 years ago

HI all, I am trying to download Partial bit streams created by Planahead , through ICAP port.The Xilinx board i am using is XUP (xc 2vp 30)....

HI all, I am trying to download Partial bit streams created by Planahead , through ICAP port.The Xilinx board i am using is XUP (xc 2vp 30). I download bitstreams into DDR ,then i am trying to transfer the bitstreams through ICAP to FPGA. All this procedure is taken care of by a program in Power PC. I am using Set Configuration function to do this job. 1. So when i try doing this the prog...


how to implement multi-port memory in FPGA?

Started by Pasacco in comp.arch.embedded14 years ago 1 reply

hi As a Xilinx dual-port memory (BRAM) user, i need to have more :) multiple port memory, for example, 8-read 4-write port memory. Some...

hi As a Xilinx dual-port memory (BRAM) user, i need to have more :) multiple port memory, for example, 8-read 4-write port memory. Some logic should wrap the memory, but i do not have idea how to implement. Does anyone point me to where i can find document or material or literature ? Thankyou


Coolrunner 2 CPLD IO

Started by Dave the Lurker in comp.arch.embedded16 years ago 6 replies

Hi, Taking advantage of a good exchange rate to the USA at present, I bought a coolrunner 2 CPLD evaluation kit from xilinx. I didn't check...

Hi, Taking advantage of a good exchange rate to the USA at present, I bought a coolrunner 2 CPLD evaluation kit from xilinx. I didn't check the IO standards of the supplied device though. I've now found it uses LVTTL amongst other things. The top end voltages of LVTTL is about mid range on standard bipolar TTL and in the linear area of CMOS. Does anyone have any experience of in...


interrupt handling using microblaze with XPS

Started by chriskoh in comp.arch.embedded13 years ago 4 replies

Hi, I am pretty new to the arena of interrupt handling and would need some help. I am currently using microblaze v4.00a and with ...

Hi, I am pretty new to the arena of interrupt handling and would need some help. I am currently using microblaze v4.00a and with Xilinx platform studio 7.1 to develop some UART handling routines. what I am not sure, is 1) whether the important registers (eg, stack pointers and other registers) are saved during an interrupt handling, or do I have to explicitly save them myself. I...


Xilinx Xilfatfs SystemACE library and partition format

Started by Anonymous in comp.arch.embedded13 years ago 1 reply

Hi, I have been struggling on a Virtex II Pro in order to make the XilFatFS work properly. What I want to do is use the Compact Flash to boot...

Hi, I have been struggling on a Virtex II Pro in order to make the XilFatFS work properly. What I want to do is use the Compact Flash to boot the board which I did successfully by formating the CF with mkdos and also gparted using the FAT 16 format. Now I also want to use the functions fOpen, chdir, mkdir and readdir from the sysace library and I tried on a FAT 32 as the primary partiti...


Crossing Clock Domains in CPLD

Started by Anonymous in comp.arch.embedded12 years ago 2 replies

Hi, Is there any smart way to pass data thru different clock domains in CPLD chips (without internal RAM for fifo) without using additional...

Hi, Is there any smart way to pass data thru different clock domains in CPLD chips (without internal RAM for fifo) without using additional chips like external async fifo ? I'm using Xilinx's XC95 chips, but I can pick something else. -- voices (at) zrgnyyvpenva (dot) pbz [ROT13]


help with interrupt catching in Xilinx EDK 9.2 and custom IP

Started by llombard in comp.arch.embedded12 years ago

Dear all, Here is my problem: I make a new microblaze project in EDK 9.2i and a new custom IP with 1 register and 2 interrupts. I leave the...

Dear all, Here is my problem: I make a new microblaze project in EDK 9.2i and a new custom IP with 1 register and 2 interrupts. I leave the default settings everywhere, I link the interrupt to the xps_intc_0 "Intr" port. I add: microblaze_enable_interrupts(); { XStatus status; print("\r\nRegistering TEST_INT_Intr_DefaultHandler() to xps_intc_0...\r\n"); status = XIntc_...


Xilinx V4 Custom IP

Started by Anonymous in comp.arch.embedded13 years ago

I am trying to write a simple custom IP to get started. I just want to control the LED on my evaluation board. I want to be able to write a...

I am trying to write a simple custom IP to get started. I just want to control the LED on my evaluation board. I want to be able to write a custom IP to prove to myself I am doing it correctly instead of using the IP provided. I am using a Memec V4 UltraController II eval board and EDK 9.1 SP2. I created a template IP using EDK and then wrote my VHDL code to control the LEDs. The proble...


ISE/EDK "target pattern contains no `%'"

Started by Anonymous in comp.arch.embedded13 years ago 2 replies

Grrrrr! Has anyone got ISE 7.1 working with EDK in Windows? Ever seen this error before? I installed ISE/EDK per instructions, and got the...

Grrrrr! Has anyone got ISE 7.1 working with EDK in Windows? Ever seen this error before? I installed ISE/EDK per instructions, and got the titular error as soon as I tried to generate a netlist inside Platform Studio. I assumed it was something stupid I did/forgot to do, so I followed the tutorial at . When I click OK on the


Ribbon cable

Started by ratemonotonic in comp.arch.embedded12 years ago

Hi all , I am relentlessly trying to integrate SMSC 91C111 with Xilinx FPGA. I have the integration working on a evaluation board , perfectly...

Hi all , I am relentlessly trying to integrate SMSC 91C111 with Xilinx FPGA. I have the integration working on a evaluation board , perfectly . Now I have a PCB spun out wiht the same circuit on the evaluation board with only the SMSC chip on it. Which I need to connect to my own board with the ribbon cable. I have varified the timing of the address and data lines (setup and hold etc) but ...


global clock (gclk) input at xilinx virtex4 fpga

Started by Denkedran Joe in comp.arch.embedded12 years ago 2 replies

Hi there, I'm using a Virtex4 FX100 FPGA (package FF1517) in a board design and I wonder if it is enough to use just one gclk input on the...

Hi there, I'm using a Virtex4 FX100 FPGA (package FF1517) in a board design and I wonder if it is enough to use just one gclk input on the device or if it's advisable to use more than one due to the large package size...? Does it make any difference where I put the gclk input(s)? Thank you for your support... Regards Joe


Maximum frequency

Started by knight in comp.arch.embedded11 years ago 2 replies

Hi all, Iam using Xilinx XST for synthesis. Iam using almost 20 modules in my design. each if i synthesize seperately iam getting a maximum...

Hi all, Iam using Xilinx XST for synthesis. Iam using almost 20 modules in my design. each if i synthesize seperately iam getting a maximum frequency of more than 400 Mhz. But when i combine everything iam getting only 121Mhz. Can you tell me the reason...??? Does this mean i cannot use a clock more than 121 Mhz in my design(iam using and found it working well..) How can i increase my...


Writing data on CF card using EDK 10.1 and xilfatfs

Started by G. Carvajal in comp.arch.embedded11 years ago

Hi there, I'm making a kind of sniffer for a small network with very low traffic. I need to capture the traffic and store the packets in...

Hi there, I'm making a kind of sniffer for a small network with very low traffic. I need to capture the traffic and store the packets in a permanent storage medium. At this time I'm using the ML403 board from Xilinx, EDK 10.1 and the xilfats library. As a preliminary test, I'm sending controlled individuals packets, and the device receive the packet and save it in a file into the CF card...