Forums Search for: Xilinx
Partial reconfiguration using ICAP
HI all, I am trying to download Partial bit streams created by Planahead , through ICAP port.The Xilinx board i am using is XUP (xc 2vp 30)....
HI all, I am trying to download Partial bit streams created by Planahead , through ICAP port.The Xilinx board i am using is XUP (xc 2vp 30). I download bitstreams into DDR ,then i am trying to transfer the bitstreams through ICAP to FPGA. All this procedure is taken care of by a program in Power PC. I am using Set Configuration function to do this job. 1. So when i try doing this the prog...
how to implement multi-port memory in FPGA?
inhi As a Xilinx dual-port memory (BRAM) user, i need to have more :) multiple port memory, for example, 8-read 4-write port memory. Some...
hi As a Xilinx dual-port memory (BRAM) user, i need to have more :) multiple port memory, for example, 8-read 4-write port memory. Some logic should wrap the memory, but i do not have idea how to implement. Does anyone point me to where i can find document or material or literature ? Thankyou
Coolrunner 2 CPLD IO
inHi, Taking advantage of a good exchange rate to the USA at present, I bought a coolrunner 2 CPLD evaluation kit from xilinx. I didn't check...
Hi, Taking advantage of a good exchange rate to the USA at present, I bought a coolrunner 2 CPLD evaluation kit from xilinx. I didn't check the IO standards of the supplied device though. I've now found it uses LVTTL amongst other things. The top end voltages of LVTTL is about mid range on standard bipolar TTL and in the linear area of CMOS. Does anyone have any experience of in...
interrupt handling using microblaze with XPS
inHi, I am pretty new to the arena of interrupt handling and would need some help. I am currently using microblaze v4.00a and with ...
Hi, I am pretty new to the arena of interrupt handling and would need some help. I am currently using microblaze v4.00a and with Xilinx platform studio 7.1 to develop some UART handling routines. what I am not sure, is 1) whether the important registers (eg, stack pointers and other registers) are saved during an interrupt handling, or do I have to explicitly save them myself. I...
Xilinx Xilfatfs SystemACE library and partition format
inHi, I have been struggling on a Virtex II Pro in order to make the XilFatFS work properly. What I want to do is use the Compact Flash to boot...
Hi, I have been struggling on a Virtex II Pro in order to make the XilFatFS work properly. What I want to do is use the Compact Flash to boot the board which I did successfully by formating the CF with mkdos and also gparted using the FAT 16 format. Now I also want to use the functions fOpen, chdir, mkdir and readdir from the sysace library and I tried on a FAT 32 as the primary partiti...
Crossing Clock Domains in CPLD
inHi, Is there any smart way to pass data thru different clock domains in CPLD chips (without internal RAM for fifo) without using additional...
Hi, Is there any smart way to pass data thru different clock domains in CPLD chips (without internal RAM for fifo) without using additional chips like external async fifo ? I'm using Xilinx's XC95 chips, but I can pick something else. -- voices (at) zrgnyyvpenva (dot) pbz [ROT13]
help with interrupt catching in Xilinx EDK 9.2 and custom IP
Dear all, Here is my problem: I make a new microblaze project in EDK 9.2i and a new custom IP with 1 register and 2 interrupts. I leave the...
Dear all, Here is my problem: I make a new microblaze project in EDK 9.2i and a new custom IP with 1 register and 2 interrupts. I leave the default settings everywhere, I link the interrupt to the xps_intc_0 "Intr" port. I add: microblaze_enable_interrupts(); { XStatus status; print("\r\nRegistering TEST_INT_Intr_DefaultHandler() to xps_intc_0...\r\n"); status = XIntc_...
Xilinx V4 Custom IP
I am trying to write a simple custom IP to get started. I just want to control the LED on my evaluation board. I want to be able to write a...
I am trying to write a simple custom IP to get started. I just want to control the LED on my evaluation board. I want to be able to write a custom IP to prove to myself I am doing it correctly instead of using the IP provided. I am using a Memec V4 UltraController II eval board and EDK 9.1 SP2. I created a template IP using EDK and then wrote my VHDL code to control the LEDs. The proble...
ISE/EDK "target pattern contains no `%'"
inGrrrrr! Has anyone got ISE 7.1 working with EDK in Windows? Ever seen this error before? I installed ISE/EDK per instructions, and got the...
Grrrrr! Has anyone got ISE 7.1 working with EDK in Windows? Ever seen this error before? I installed ISE/EDK per instructions, and got the titular error as soon as I tried to generate a netlist inside Platform Studio. I assumed it was something stupid I did/forgot to do, so I followed the tutorial at . When I click OK on the
global clock (gclk) input at xilinx virtex4 fpga
inHi there, I'm using a Virtex4 FX100 FPGA (package FF1517) in a board design and I wonder if it is enough to use just one gclk input on the...
Hi there, I'm using a Virtex4 FX100 FPGA (package FF1517) in a board design and I wonder if it is enough to use just one gclk input on the device or if it's advisable to use more than one due to the large package size...? Does it make any difference where I put the gclk input(s)? Thank you for your support... Regards Joe
Maximum frequency
inHi all, Iam using Xilinx XST for synthesis. Iam using almost 20 modules in my design. each if i synthesize seperately iam getting a maximum...
Hi all, Iam using Xilinx XST for synthesis. Iam using almost 20 modules in my design. each if i synthesize seperately iam getting a maximum frequency of more than 400 Mhz. But when i combine everything iam getting only 121Mhz. Can you tell me the reason...??? Does this mean i cannot use a clock more than 121 Mhz in my design(iam using and found it working well..) How can i increase my...
Writing data on CF card using EDK 10.1 and xilfatfs
Hi there, I'm making a kind of sniffer for a small network with very low traffic. I need to capture the traffic and store the packets in...
Hi there, I'm making a kind of sniffer for a small network with very low traffic. I need to capture the traffic and store the packets in a permanent storage medium. At this time I'm using the ML403 board from Xilinx, EDK 10.1 and the xilfats library. As a preliminary test, I'm sending controlled individuals packets, and the device receive the packet and save it in a file into the CF card...
Nuhorizons Spartan-3 board with Ethernet?
inDoes anybody know whether the Nuhorizons board (http://www.nuhorizons.com/products/xilinx/spartan3/development-board.html) can be interfaced...
Does anybody know whether the Nuhorizons board (http://www.nuhorizons.com/products/xilinx/spartan3/development-board.html) can be interfaced (easily) with the NET1 Ethernet peripheral board from Digilent? (https://digilent.us/Sales/Peripheral.cfm) If so, could someone explain how it would be done? cheers, C3
Graphical User Interface project on Spartan-3 FPGA
inI am a student of Electronics and I am going to do semester work on the topic "Implementation of Graphical User Interfaces on an Embedded...
I am a student of Electronics and I am going to do semester work on the topic "Implementation of Graphical User Interfaces on an Embedded Platform". We are allowed to choose a project of our own so this is why I am currently looking for suitable project ideas. The work shall be implemented on a Xilinx Spartan-3A/3AN Starter Kit Board, making use of the Microblaze CPU. As most important ...
Debugging DDR3 - refresh signal oddness on DQS
inHi, We're trying to debug a new board with failing DDR3. It's a Xilinx Zynq chip with an ARM Cortex A9 dual core, and built in DDR...
Hi, We're trying to debug a new board with failing DDR3. It's a Xilinx Zynq chip with an ARM Cortex A9 dual core, and built in DDR interface/controller/phy. We've scoped up the differential DQS lines and are using JTAG to perform reads and writes but there's a lot of unexplained traffic on the line. Every 7.8us (i.e. tREFI for the DDR) we see a burst of 33 pulses on the DQS (i.e. 64 ...
which low cost fpga for space?
inI want to design a space system and don't want to use airspace expensive fpga. considering space radiation I want to make this system fault...
I want to design a space system and don't want to use airspace expensive fpga. considering space radiation I want to make this system fault tolerant. ACTEL is flash-based but in program lost condition ( even with low probability ) it should be reprogrammed so a programing circuit is also needed. Xilinx or Altera are RAMbased but they have very small size EPROMs to store both hardware configur...
microblaze and flash access
Hi, I am trying to access a flash device from a microblaze processor on a Spartan 3E device. In Xilinx XPS, I instantiated the IP...
Hi, I am trying to access a flash device from a microblaze processor on a Spartan 3E device. In Xilinx XPS, I instantiated the IP "External Memory Controller" with the following attributes BEGIN xps_mch_emc PARAMETER INSTANCE = flash_16Mx8b PARAMETER HW_VER = 2.00.a PARAMETER C_NUM_BANKS_MEM = 1 PARAMETER C_NUM_CHANNELS = 0 PARAMETER C_MEM0_WIDTH = 8 PARAMETER C_MAX_MEM_WIDTH = ...
SoC from Microsemi - FPGA and ARM CM3
inI know Xilinx and Altera have their SoC devices which are a bit high end with dual A9 type ARMs. I recently found out the Microsemi SoC which...
I know Xilinx and Altera have their SoC devices which are a bit high end with dual A9 type ARMs. I recently found out the Microsemi SoC which uses a CM3 can be bought for just $16 and a KickStart board is available for just $59. I like it. The FPGA fabric is flash based rather than SRAM so you don't need to configure it each time it powers up. The CPU has up to 512 kB flash and 144...
FPGA based processor vs. "hard" processor
inI just finish reading the interesting thread of PIC vs AVR. I am not in the embedded area but have a related question. In recent...
I just finish reading the interesting thread of PIC vs AVR. I am not in the embedded area but have a related question. In recent Xilinx marketing stuff for Spartan-3 FPGA, it indicates that the 100K-gate FPGA now reaches $2 a piece, and the costs of softcore 8-bit processor (PicoBlaze) and 32-bit processor (MicroBlaze) are reduced to $0.10 and $0.48. Despite of the marketing hype, do you...
ethernet - DP83847 PROBLEM
inHello Everyone, I have few questions regarding the DP83847 PHY. I have this PHY on xilinx virtex fpga board. I need to write an ethernet mac...
Hello Everyone, I have few questions regarding the DP83847 PHY. I have this PHY on xilinx virtex fpga board. I need to write an ethernet mac in the fpga to send the packets to the PC through the PHY. Initially, to start with i am implementing the transmit module. 1) when i hardware reset the PHY, the link estabilishes between the PC and the fpga board, but whatever data i put on the MII ...