Forums Search for: Xilinx
driver allowing to define GPIO pin groups and control them via sysfs
Hi, I'm developing a system based on Xilinx MPSoC chip, where multiple functionalities are controlled by AXI GPIO blocks. All those GPIO pins...
Hi, I'm developing a system based on Xilinx MPSoC chip, where multiple functionalities are controlled by AXI GPIO blocks. All those GPIO pins are accessible via sysfs interface. However, it is difficult to find the gpio chip and pin numbers from running Linux system. In the HDL design, the GPIO blocks are described by their names, but unfortunately those names are not propagated to
Cypress FX2 bandwidth problem
We have developed data acquisition system which uses Cypress FX2 as the USB 2.0 interface. State machine for control and conversion of data...
We have developed data acquisition system which uses Cypress FX2 as the USB 2.0 interface. State machine for control and conversion of data between AD converters and FX2 is implemented using Xilinx Spartan 2 FPGA. The problem is that with higher data rates (up to 25 Mbit/s) we experience FX2 internal FIFO stalls and missing data on the receiving side. Small FIFO implemented inside FPGA d...
xilinx Flash interface
Hi, In my design I want to use the compact flash interface to my processor in FPGA. In the development board ACE controller is in between...
Hi, In my design I want to use the compact flash interface to my processor in FPGA. In the development board ACE controller is in between compact Flash and processor. I think the power PC access the ace controller for all read of Flash. Are there anyways I can make this flash as just memory device (PROM), and access without ACE controller. I'd seen some articles saying usage of flash as non ...
Help with OV7620 sensor connected to FPGA
I'm trying to implement an OV7620 sensor on a Spartan 3 (Xilinx FPGA) to display on VGA, the problem is to syncronize the sensor data with...
I'm trying to implement an OV7620 sensor on a Spartan 3 (Xilinx FPGA) to display on VGA, the problem is to syncronize the sensor data with VGA exit. The sensor is already programed to send data in progressive mode by 2 channels: channel Y G G G G channel UV B R B R Please, somebody can tell me how to syncronize with a monitor to display data on VGA? Regards!!!
Embedded USB webcam IDENTIFIER hardware
Hi, I need to develop a embedded hardware (with a FPGA, example Xilinx(R) Spartan-3AN FPGA) capable of IDENTIFY what kind of USB web cam...
Hi, I need to develop a embedded hardware (with a FPGA, example Xilinx(R) Spartan-3AN FPGA) capable of IDENTIFY what kind of USB web cam is plugged-in (example webcam manufacturer, speed, data transfer rate, etc.), the USB will work with USB 1.0 or USB 1.1 (not USB 2.0) so a USB 2.0 web cam will work at USB 1.1. Due this is a embedded design, no computer interaction is required (this means that th...
cutting down opb_clk cycles while read-write BRAM-DDR in FPGA
Hello all, I am working on a project which involves a simple BRAM, OPB-PLB, Microblaze/PPC, and opb_ddr_sdram controller. I am reading 1280...
Hello all, I am working on a project which involves a simple BRAM, OPB-PLB, Microblaze/PPC, and opb_ddr_sdram controller. I am reading 1280 bytes of data from bram (32 bits each read, thus a total of 320 reads) and writing it to DDR sdram. i am using Xilinx standalone OS. i use the command XIo_in32(addr) to read from bram and use XIo_out32(addr,data) to write to DDR sdram controller. h...
Create Peripheral in XPS / FIFO debug on ChipScope
SW env. ISE8.1 / XPS8.1 / ModelSim / ChipScope 60day ver HW env. Xilinx virtex2pro xs2vp30 My lab usually work in XPS and ModelSim for Create...
SW env. ISE8.1 / XPS8.1 / ModelSim / ChipScope 60day ver HW env. Xilinx virtex2pro xs2vp30 My lab usually work in XPS and ModelSim for Create Embedded IP creation. Mostly we use FIFO unit in IP, so it works only when the data packet was pushed. Until last week out PhD says to do simulation in ModelSim. But now we have to debug by ChipScope I made my IP could work only when data is pushed...
Create Peripheral in XPS / FIFO debug on ChipScope
SW env. ISE8.1 / XPS8.1 / ModelSim / ChipScope 60day ver HW env. Xilinx virtex2pro xs2vp30 My lab usually work in XPS and ModelSim for Create...
SW env. ISE8.1 / XPS8.1 / ModelSim / ChipScope 60day ver HW env. Xilinx virtex2pro xs2vp30 My lab usually work in XPS and ModelSim for Create Embedded IP creation. Mostly we use FIFO unit in IP, so it works only when the data packet was pushed. Until last week out PhD says to do simulation in ModelSim. But now we have to debug by ChipScope I made my IP could work only when data is pushed...
Create Peripheral in XPS / FIFO debug on ChipScope
SW env. ISE8.1 / XPS8.1 / ModelSim / ChipScope 60day ver HW env. Xilinx virtex2pro xs2vp30 My lab usually work in XPS and ModelSim for Create...
SW env. ISE8.1 / XPS8.1 / ModelSim / ChipScope 60day ver HW env. Xilinx virtex2pro xs2vp30 My lab usually work in XPS and ModelSim for Create Embedded IP creation. Mostly we use FIFO unit in IP, so it works only when the data packet was pushed. Until last week out PhD says to do simulation in ModelSim. But now we have to debug by ChipScope I made my IP could work only when data is pushed...
Compilation of Plasma SW under Linux
Hi All, I have successfully compiled the Plasma soft CPU for my Xilinx Spartan 3E Starter Kit (the version of Plasma...
Hi All, I have successfully compiled the Plasma soft CPU for my Xilinx Spartan 3E Starter Kit (the version of Plasma core http://www.opencores.org/projects.cgi/web/mips/overview contains the top entity and UCF needed for this board). However I was not able to generate my own software for this CPU. The provided tools ( http://www.opencores.org/projects.cgi/web/mips/gccmips_elf.zip, htt...
How could i play svf file correctly ?
Hi folks, When trying to execute my SVF file , Impact software provided by Xilinx issues errors like : ScanDR 32 TDI(00000000) TDO(F286E093)...
Hi folks, When trying to execute my SVF file , Impact software provided by Xilinx issues errors like : ScanDR 32 TDI(00000000) TDO(F286E093) Mask(0FFFFFFF) Smask(FFFFFFFF) ERROR:iMPACT - Failed ScanDR: TDO does not match Expected TDO ERROR:iMPACT - TDO ReadBack : 00000001 ERROR:iMPACT - TDO Expected : f286e093 EXCEPTION:iMPACT:SVFReader.c:335:1.20.14.1 - Scan Data Mismatch. INFO:iMPACT...
Low cost solution to program Spartan 3AN DSP development board AES-SPEEDWAY-S3ADSP-SK Opzioni
I'm trying to renew my experience on fpga so last week I buy a Spartan 3AN DSP development board AES-SPEEDWAY-S3ADSP-SK from Silica for about...
I'm trying to renew my experience on fpga so last week I buy a Spartan 3AN DSP development board AES-SPEEDWAY-S3ADSP-SK from Silica for about 235euro. But I've not the cable to program it, so I ask to Silica that suggest me the http://www.xilinx.com/products/devkits/HW-USB-G.htm for 140 euros but my budget for personal training is ended, can you suggest me some cheaper solution to program t...
Xilinx EDK inferred dual port BRAM unconnected clkb
As part of an edk peripheral i have inferred 2 dual port BRAMs which synthesise and simulate correctly For both BRAMs port a is controlled by...
As part of an edk peripheral i have inferred 2 dual port BRAMs which synthesise and simulate correctly For both BRAMs port a is controlled by the microblaze port b is controlled by fsm BRAM 1 is used for PLB to peripheral communication in this case the input to port b data_in is never used or assigned BRAM 2 is used for peripheral to PLB communication in this case the input to port b...
