Unable to generate NIOS II

Started by syyang85 in FPGA-CPU10 years ago 1 reply

Hi all, I'm using Altera Quartus 2 6.1 and the board that I'm using is UP3 development board from Altera. I'm opening the example of Nios...

Hi all, I'm using Altera Quartus 2 6.1 and the board that I'm using is UP3 development board from Altera. I'm opening the example of Nios II system made by Altera. But i get the following error when I try to generate it. What error is this? On the other hand, what is the best way to save a stream of data into SDRAM? or would it be better if I made a soft memory for this purpose? Rega...


TO_UNSIGNED command in vhdl

Started by siva...@gmail.com in FPGA-CPU10 years ago 1 reply

hi, any one please tell me, the use of commands TO_UNSIGNED, TO_INTEGER,TO_SIGNED in vhdl language. To post a message, send it to:...

hi, any one please tell me, the use of commands TO_UNSIGNED, TO_INTEGER,TO_SIGNED in vhdl language. To post a message, send it to: f...@yahoogroups.com To unsubscribe, send a blank message to: f...@yahoogroups.com


DWT in vhdl

Started by siva...@gmail.com in FPGA-CPU10 years ago 3 replies

hi, how to implement discrete wavelet transform for image compression in vhdl.plz. give me brief idea. if anyone has source code please send...

hi, how to implement discrete wavelet transform for image compression in vhdl.plz. give me brief idea. if anyone has source code please send to me. thank you To post a message, send it to: f...@yahoogroups.com To unsubscribe, send a blank message to: f...@yahoogroups.com


how to send image information in to fpga kit

Started by siva...@gmail.com in FPGA-CPU10 years ago 1 reply

hi i am doing image compression using discrete wavelet transformation. it is a hard ware implementation . i am using spartanII...

hi i am doing image compression using discrete wavelet transformation. it is a hard ware implementation . i am using spartanII fpga kit. but i dont i know how to send image information in to fpga kit. does any one know tell me. thank you To post a message, send it to: f...@yahoogroups.com To unsubscribe, send a blank message to: f...@yahoogrou...


Frame Grabber using FPGA thru webcam

Started by syyang85 in FPGA-CPU10 years ago 36 replies

Hello, I'm a student doing a project on implementing optical flow algorithm into FPGA. Basically, i would like to mount a camera ( preferably...

Hello, I'm a student doing a project on implementing optical flow algorithm into FPGA. Basically, i would like to mount a camera ( preferably webcam coz its cheap) onto a FPGA( my college currently has up2 and up3 @ltera education board) and it do some image/video processing in FPGA and display in an LCD or CRT monitor. As for my part, I'm doing the input part. That is getting the data...


Inferred Priority Encoder In VHDL

Started by rtstofer in FPGA-CPU11 years ago 12 replies

Consider something like: result

Consider something like: result


use C++ int__64 type variables in NIOS IDE

Started by paria354 in FPGA-CPU11 years ago 1 reply

does anyone know how to use C++ int__64 type variables when we want to implement it on NIOS IDE? coz IDE doesn't support upper than 32 bit...

does anyone know how to use C++ int__64 type variables when we want to implement it on NIOS IDE? coz IDE doesn't support upper than 32 bit integers.how can we use them in a big and intricate code. I mean that we can not devide all of the 64 bit variables into two 32 bit.coz the C++ code is very complex and it has lots of this type variables. To post a message, send it to: f...@yahoogro...


Hirose FX2 Backplane ?

Started by Rob Finch in FPGA-CPU11 years ago 5 replies

Is there a Hirose FX2 100 pin backplane or cabling available ? I'd like to connect some Nexys boards together. Robert To post a message,...

Is there a Hirose FX2 100 pin backplane or cabling available ? I'd like to connect some Nexys boards together. Robert To post a message, send it to: f...@yahoogroups.com To unsubscribe, send a blank message to: f...@yahoogroups.com


Re: FPGA routing - was - Re: POP-11 (PDP-11/40 in an FPGA)

Started by woodelf in FPGA-CPU11 years ago 3 replies

Austin Franklin wrote: > I'm not sure how long it's been since you've done any FPGA work, but though > that was true up through the 3k and...

Austin Franklin wrote: > I'm not sure how long it's been since you've done any FPGA work, but though > that was true up through the 3k and less true with the 4k series of Xilinx > parts, the later serieses have far more routing resources, and routing is > typically not an issue, especially for complex designs. Why does everybody assume Xilinx is the *only* brand of FPGA's. I used Altera


POP-11 (PDP-11/40 in an FPGA)

Started by Scott in FPGA-CPU11 years ago 94 replies

Hello, I came across this old posting for the POP-11, but the original URL no longer works. I'd really like to get the VHDL source code for...

Hello, I came across this old posting for the POP-11, but the original URL no longer works. I'd really like to get the VHDL source code for the POP-11 project if possible. Can someone send me an updated URL? Thanks in Advance, Scott -- In Oct 6, 2004, Naohiko Shimizu-san wrote: > > Hi all, > > I and my student Mr.Iida placed a PDP11/40 compatible CPU source > code on our web site.


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