Is there a Hirose FX2 100 pin backplane or cabling available ? I'd like to connect some Nexys boards together. Robert To post a message,...

Is there a Hirose FX2 100 pin backplane or cabling available ? I'd like to connect some Nexys boards together. Robert To post a message, send it to: f...@yahoogroups.com To unsubscribe, send a blank message to: f...@yahoogroups.com

Hello, I came across this old posting for the POP-11, but the original URL no longer works. I'd really like to get the VHDL source code for...

Hello, I came across this old posting for the POP-11, but the original URL no longer works. I'd really like to get the VHDL source code for the POP-11 project if possible. Can someone send me an updated URL? Thanks in Advance, Scott -- In Oct 6, 2004, Naohiko Shimizu-san wrote: > > Hi all, > > I and my student Mr.Iida placed a PDP11/40 compatible CPU source > code on our web site.

Good morning I have a project where I need to embed microcontroller in a Xilinx ML401.This project consist a GSM which connect to a...

Good morning I have a project where I need to embed microcontroller in a Xilinx ML401.This project consist a GSM which connect to a microcontroller(ATMEGA8535) and the microcontroller is eventually connected to Xilinx Virtex4 (ML401).It is actually road traffic light implementation for Emergency Vehicle Preemption System. My friend told me that I could do this by implementing a Microbl...

Trying to understand the LAB wide sload and sclear signals better, I happend upon this gem by Paul Metzgen:...

Trying to understand the LAB wide sload and sclear signals better, I happend upon this gem by Paul Metzgen: http://www.cs.tut.fi/soc/Metzgen04.pdf (I wish I had attended this talk). Among other things, he shows how on Stratix/Cyclone, a single LE can implement (assuming sclear and sload is shared between all LE in a LAB) if (sclear) q

Hi, I want to introduce myself as new member of the list, and take advantage of the opportunity to ask a question about Digilent's...

Hi, I want to introduce myself as new member of the list, and take advantage of the opportunity to ask a question about Digilent's Nexys Spartan 3 board. I purchase the 1000k gate version. I would like to use the off-chip memory and tough that a good place to start was the build-in self test sources that the company provide in their web site. However, I get error when I try to re-synthesiz...

What's new with the new multi-context processor patent ? http://www.freepatentsonline.com/5872985.html To post a message, send it to:...

What's new with the new multi-context processor patent ? http://www.freepatentsonline.com/5872985.html To post a message, send it to: f...@yahoogroups.com To unsubscribe, send a blank message to: f...@yahoogroups.com

Hi All, I'm new to fpga design and was trying to research on logic on how to implement several memory mapped registers on an FPGA. I'm trying...

Hi All, I'm new to fpga design and was trying to research on logic on how to implement several memory mapped registers on an FPGA. I'm trying not to take shortcuts by relying on the FPGA tool to make them for me, because I want to know how it's put together. I was thinking that it might consist of several decoders which generate signals that go the appropriate latches to store the data o

After implementing the Wishbone interface for main memory access from JOP I see several issues with the Wishbone specification that makes...

After implementing the Wishbone interface for main memory access from JOP I see several issues with the Wishbone specification that makes it not the best choice for SoC interconnect. The Wishbone interface specification is still in the tradition of microcomputer or backplane busses. However, for a SoC interconnect, which is usually point-to-point, this is

Just a notice to anyone playing with the System09 VHDL core, There are a few updates to the CPU09 core. JSR [0,S] did not work...

Just a notice to anyone playing with the System09 VHDL core, There are a few updates to the CPU09 core. JSR [0,S] did not work properly The stack pointer was pre-decremented ready to push the return address before the indexed effective address was calculated. EXG xx,CC and TFR xx,CC did not work properley. The ALU did not transfer

ST's new reconfigurable microcontroller with dual mac dsp which has 16MBit DRAM, 300MHz ARM9, 600MHZ DSP, and a 150K FPGA, Dual...

ST's new reconfigurable microcontroller with dual mac dsp which has 16MBit DRAM, 300MHz ARM9, 600MHZ DSP, and a 150K FPGA, Dual ethernet, ADC/DAC.... http://www.st.com/stonline/books/as cii/docs/11335.htm Taken their existing STW21000 - ARM926 + fpga and added to it.