Forums More fpga-cpu
Experiences with the Altera UP3-board and NiosII
inHi, I was wondering if anyone has experiences using the Altera UP3-board with NiosII? Any comments are welcome. I'm looking...
Hi, I was wondering if anyone has experiences using the Altera UP3-board with NiosII? Any comments are welcome. I'm looking for an educational board suitable for microprocessor designs and this seems to have the right peripherals.
New to FPGA development
inHey guys (newby here), I am looking for a cheep development board with a few cool additions on it. My sole reason (one...
Hey guys (newby here), I am looking for a cheep development board with a few cool additions on it. My sole reason (one of them anyway) is to move from coding that we do in class (3rd year, EE) to the actual development of home projects that I can keep.
Java JTAG API
inI found the Java JTAG API that I was talking about. It is called JavaScan and has been withdrawn. ...
I found the Java JTAG API that I was talking about. It is called JavaScan and has been withdrawn. http://www.jcp.org/en/jsr/detail?id=2 (inkludes example source code to program a XC9500) There is a HAL that allows to efficien
simulation libraries
inI'm trying to simulate a design and I need the Xilinx block ram instances and CLKDLL to simulate. But they aren't included in ...
I'm trying to simulate a design and I need the Xilinx block ram instances and CLKDLL to simulate. But they aren't included in ModelSim by default. I tried to add the libraries from the Xilinx directory, but the OK button in the ModelSim add library dialog is greyed out. Do
Xilinx vs Altera / Microblaze vs Nios???
inWe are in the process of selecting an FPGA board for a series of laborations in courses ranging from computer engineering,...
We are in the process of selecting an FPGA board for a series of laborations in courses ranging from computer engineering, embedded software development to VHDL design, SoC architectures and operating systems. We are trying to evaluate Xilinx vs Altera boards
ANN: Introducing MANIK - a 32 bit Soft-Core RISC Processor
inhttp://www.niktech.com Hardware Features ? Data Path Width 32 bits ? Most instructions are 16 bit. PC Relative...
http://www.niktech.com Hardware Features ? Data Path Width 32 bits ? Most instructions are 16 bit. PC Relative jump instructions are 32 bit. ? Four stage pipeline. ? Von Neumann Architecture (Data and Instr
soft ip processors? history? advantages? vs ucontroller?
inSir, Soft IP Processors (my questions is from fpga prospective not from asic) have made strong hold in market, several...
Sir, Soft IP Processors (my questions is from fpga prospective not from asic) have made strong hold in market, several vendors like Xilinx(Picoblaze & Microblaze), @ltera(NIOS and NIOS-II) are making them. please do me a favor, I require some documents (articles
building xr16 lcc compiler
inHas anyone tried building the xr16 lcc 'C' compiler using visual c++ version 7, instead of version 6 ? It seems to build...
Has anyone tried building the xr16 lcc 'C' compiler using visual c++
version 7, instead of version 6 ?
It seems to build everything fine, but the resulting compiler croaks
with the message
#line 1 "
Execution unit in Verilog ?
inDear helper, I am implementing a new processor in verilog. I am no near the execution unit implementation!! Does any one have...
Dear helper, I am implementing a new processor in verilog. I am no near the execution unit implementation!! Does any one have (or know) a full design of RISC-style instructions execution unit in verilog. I am planning to implement 1 ALU unit, 1 Branch unit, 1 SET unit, and 1
related to 16-bit fpga cpu development
inFirst of all thanks for reply. Well I want to mimic the Mr.Gray's x16 and MIPS(as discribed in "Computer Organization and...
First of all thanks for reply. Well I want to mimic the Mr.Gray's x16 and MIPS(as discribed in "Computer Organization and Design The Hardware/Software Interface", 2nd Ed By David Patterson and John Hennessy). My Constraint is that I specified in project propo
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