Re: RAM loading via JTAG

Started by Piotr Zbysinski - EP\\H\\ in FPGA-CPU12 years ago 6 replies

----- Original Message ----- From: Richard Duits To: lpc2000@lpc2... Sent: Thursday, August 18, 2005 1:15 AM Subject: Re:...

----- Original Message ----- From: Richard Duits To: lpc2000@lpc2... Sent: Thursday, August 18, 2005 1:15 AM Subject: Re: [lpc2000] RAM loading via JTAG When you switch the ARM7 into debug mode, all instructions and data are read from the jtag interface. You can just upload a ldm instruction for example with the data followin


ST's new reconfigurable microcontroller

Started by Alex Gibson in FPGA-CPU13 years ago 13 replies

ST's new reconfigurable microcontroller with dual mac dsp which has 16MBit DRAM, 300MHz ARM9, 600MHZ DSP, and a 150K FPGA, Dual...

ST's new reconfigurable microcontroller with dual mac dsp which has 16MBit DRAM, 300MHz ARM9, 600MHZ DSP, and a 150K FPGA, Dual ethernet, ADC/DAC.... http://www.st.com/stonline/books/as cii/docs/11335.htm Taken their existing STW21000 - ARM926 + fpga and added to it.


Optimal Hardware Implementation FIFO/LRU/Random Algos

Started by invincible1138 in FPGA-CPU13 years ago 4 replies

Hi all! I want to know the most optimal way to implement FIFO/LRU/Random in hardware. I am designing a cache and i need to implement...

Hi all! I want to know the most optimal way to implement FIFO/LRU/Random in hardware. I am designing a cache and i need to implement these as replacement algorithms. I guess this makes clear why i want a fast hardware solution for implementing these. regards, mnsharif


CISC architecture processor in vhdl & then in fpga (LeonardoSpectrum - ModelSim)

Started by xrisas1 in FPGA-CPU13 years ago 1 reply

I'm a student.I'm now learning VHDL. Help. I'm looking for a generic vhdl library. Registers,ALU,Shifter,RAM,SubSequencer. ...

I'm a student.I'm now learning VHDL. Help. I'm looking for a generic vhdl library. Registers,ALU,Shifter,RAM,SubSequencer. HELP. Implementing CISC architecture processor in Book : Computer Designs Funtamentals, Morris Mano HELP


anyone has ps2 keyboard controller cores?

Started by cationebox in FPGA-CPU13 years ago 2 replies

can anyone help me ? i will use it in my project but i am not sure to write right code in time so i turn to you can you help me...

can anyone help me ? i will use it in my project but i am not sure to write right code in time so i turn to you can you help me ? vhdl is better than in verilog thanks a lot


Use for 2 bit opcode ?

Started by Rob Finch in FPGA-CPU13 years ago 17 replies

Can anyone think of a use for a two bit opcode ? It all started when I decided to use a 42 bit code. Three opcodes are packed into...

Can anyone think of a use for a two bit opcode ? It all started when I decided to use a 42 bit code. Three opcodes are packed into 128 bits, but that leaves 2 bits left over, so what can I do with them ?


transputer fpga

Started by Alex Gibson in FPGA-CPU13 years ago

Spotted this in comp.arch.transputer and in comp.arch.fpga by johnjakson JJ dated 02/04/2005 (yes 2nd of April) Announcement This...

Spotted this in comp.arch.transputer and in comp.arch.fpga by johnjakson JJ dated 02/04/2005 (yes 2nd of April) Announcement This first partial release date was chosen to be April 1st, to suggest some light hearted foolery here and to force myself to get something out to show for a couple years of work. Indeed the joke is really on all


bit serial CPUs, anyone?

Started by Jan Gray in FPGA-CPU13 years ago 8 replies

See http://wiki.openchip.org/index.php/Cont est:SRL16. I've been waiting for some tiny bit-serial CPUs to emerge. This is your chance...

See http://wiki.openchip.org/index.php/Cont est:SRL16. I've been waiting for some tiny bit-serial CPUs to emerge. This is your chance at fame! (Well, what passes for fame on comp.arch.fpga.) :-) I think it would be most impressive if your CPU was C programmable and it could run a C simulation of itself.


Ideas For Array Processor

Started by rtstofer in FPGA-CPU13 years ago 4 replies

I am looking into the idea of a maze solving robot. The flood fill algorithm (see ...

I am looking into the idea of a maze solving robot. The flood fill algorithm (see http://micromouse.cannock.ac.uk/ maze/fastfloodsolver.htm ) is simple enough but takes a lot of time when serially programmed on


strange register behavior in Verilog blocks under Quartus II

Started by lionheart_99_de in FPGA-CPU13 years ago

Hello, I'm quite new to FPGAs and SoC Design. My original working area was hig level simulation and SW programming. To get...

Hello, I'm quite new to FPGAs and SoC Design. My original working area was hig level simulation and SW programming. To get an insight of FPGA and SoC design I downloaded the risc16f84 IP core from opencores.org and tried to get the small version of the PIC16F84 running on our an Altera FPGA board with a Flex 10K FPGA using th


Ask a Question to the EmbeddedRelated community

To significantly increase your chances of receiving answers, please make sure to:

  1. Use a meaningful title
  2. Express your question clearly and well
  3. Do not use this forum to promote your product, service or business
  4. Write in clear, grammatical, correctly-spelled language
  5. Do not post content that violates a copyright