Experiences with the Altera UP3-board and NiosII

Started by Mats Brorsson in FPGA-CPU16 years ago 3 replies

Hi, I was wondering if anyone has experiences using the Altera UP3-board with NiosII? Any comments are welcome. I'm looking...

Hi, I was wondering if anyone has experiences using the Altera UP3-board with NiosII? Any comments are welcome. I'm looking for an educational board suitable for microprocessor designs and this seems to have the right peripherals.


New to FPGA development

Started by sirtiffguy in FPGA-CPU17 years ago 15 replies

Hey guys (newby here), I am looking for a cheep development board with a few cool additions on it. My sole reason (one...

Hey guys (newby here), I am looking for a cheep development board with a few cool additions on it. My sole reason (one of them anyway) is to move from coding that we do in class (3rd year, EE) to the actual development of home projects that I can keep.


Java JTAG API

Started by Kolja Sulimma in FPGA-CPU17 years ago 5 replies

I found the Java JTAG API that I was talking about. It is called JavaScan and has been withdrawn. ...

I found the Java JTAG API that I was talking about. It is called JavaScan and has been withdrawn. http://www.jcp.org/en/jsr/detail?id=2 (inkludes example source code to program a XC9500) There is a HAL that allows to efficien


simulation libraries

Started by Rob Finch in FPGA-CPU17 years ago 2 replies

I'm trying to simulate a design and I need the Xilinx block ram instances and CLKDLL to simulate. But they aren't included in ...

I'm trying to simulate a design and I need the Xilinx block ram instances and CLKDLL to simulate. But they aren't included in ModelSim by default. I tried to add the libraries from the Xilinx directory, but the OK button in the ModelSim add library dialog is greyed out. Do


Xilinx vs Altera / Microblaze vs Nios???

Started by Mats Brorsson in FPGA-CPU17 years ago 14 replies

We are in the process of selecting an FPGA board for a series of laborations in courses ranging from computer engineering,...

We are in the process of selecting an FPGA board for a series of laborations in courses ranging from computer engineering, embedded software development to VHDL design, SoC architectures and operating systems. We are trying to evaluate Xilinx vs Altera boards


ANN: Introducing MANIK - a 32 bit Soft-Core RISC Processor

Started by sandeep94404 in FPGA-CPU17 years ago 1 reply

http://www.niktech.com Hardware Features ? Data Path Width 32 bits ? Most instructions are 16 bit. PC Relative...

http://www.niktech.com Hardware Features ? Data Path Width 32 bits ? Most instructions are 16 bit. PC Relative jump instructions are 32 bit. ? Four stage pipeline. ? Von Neumann Architecture (Data and Instr


soft ip processors? history? advantages? vs ucontroller?

Started by umairsiddiqui0800 in FPGA-CPU17 years ago 2 replies

Sir, Soft IP Processors (my questions is from fpga prospective not from asic) have made strong hold in market, several...

Sir, Soft IP Processors (my questions is from fpga prospective not from asic) have made strong hold in market, several vendors like Xilinx(Picoblaze & Microblaze), @ltera(NIOS and NIOS-II) are making them. please do me a favor, I require some documents (articles


building xr16 lcc compiler

Started by Rob Finch in FPGA-CPU17 years ago 7 replies

Has anyone tried building the xr16 lcc 'C' compiler using visual c++ version 7, instead of version 6 ? It seems to build...

Has anyone tried building the xr16 lcc 'C' compiler using visual c++ version 7, instead of version 6 ? It seems to build everything fine, but the resulting compiler croaks with the message #line 1 "" when you try to compile s


Execution unit in Verilog ?

Started by Ben A. Abderazek in FPGA-CPU17 years ago 3 replies

Dear helper, I am implementing a new processor in verilog. I am no near the execution unit implementation!! Does any one have...

Dear helper, I am implementing a new processor in verilog. I am no near the execution unit implementation!! Does any one have (or know) a full design of RISC-style instructions execution unit in verilog. I am planning to implement 1 ALU unit, 1 Branch unit, 1 SET unit, and 1


related to 16-bit fpga cpu development

Started by Umair siddiqui in FPGA-CPU17 years ago 11 replies

First of all thanks for reply. Well I want to mimic the Mr.Gray's x16 and MIPS(as discribed in "Computer Organization and...

First of all thanks for reply. Well I want to mimic the Mr.Gray's x16 and MIPS(as discribed in "Computer Organization and Design The Hardware/Software Interface", 2nd Ed By David Patterson and John Hennessy). My Constraint is that I specified in project propo


Ask a Question to the EmbeddedRelated community

To significantly increase your chances of receiving answers, please make sure to:

  1. Use a meaningful title
  2. Express your question clearly and well
  3. Do not use this forum to promote your product, service or business
  4. Write in clear, grammatical, correctly-spelled language
  5. Do not post content that violates a copyright