I'm a final year computer science student at the University of Bristol, England. I am currently doing research for my final year ...

I'm a final year computer science student at the University of Bristol, England. I am currently doing research for my final year project titled "Writing an instruction stream generator for a DUV". Currently, I am having problems finding a DUV. Could anyone tell me

Ken Seefried wrote: > Has anyone done an FPGA model for the PDP-11 instruction set? > The PDP 11 is still being produced but...

Ken Seefried wrote: > Has anyone done an FPGA model for the PDP-11 instruction set? > The PDP 11 is still being produced but not by DEC or who ever owns them now, so the instruction set is still copywrite.

Hi, friends, I am doing a design work of assigning as many XR-16 CPUs on a Altera development board to see the performance (the...

Hi, friends, I am doing a design work of assigning as many XR-16 CPUs on a Altera development board to see the performance (the clock cycles of a specific C program). Those who also do the similiar work of multi-cpu (XR-16) design: please give me your kind advice and share some useful ex

If somebody needs a complete 6805 core, only send me an email; I'll be happy to share my design. It's a complete 6805 core (207...

If somebody needs a complete 6805 core, only send me an email; I'll be happy to share my design. It's a complete 6805 core (207 instructions, including MUL). Only 2 drawbacks: a) comments and an associated paper are written in Spanish. b) it's written using ALTERA AHDL, target

Hi, I am new to FPGA design. I am learning verilog and modelsim now. I want to implement my design for personal interest in...

Hi, I am new to FPGA design. I am learning verilog and modelsim now. I want to implement my design for personal interest in future. Any company of FPGA is OK for me. The most important is not expensive and easy to get the resource personally (eg. FPGA, download cable, programmer....

Hi All, Does anyone here use a meta-assembler or retargettable assembler? If not what is the expected form of software development...

Hi All, Does anyone here use a meta-assembler or retargettable assembler? If not what is the expected form of software development - do you code directly in machine code or maybe create lots of macros in some other non-relevent assembler? Regards Sergio

Dear all, any one know how to design a 16X16 multiplier with one clock cycle? I know that some FPGA support embedded 16 X 16...

Dear all, any one know how to design a 16X16 multiplier with one clock cycle? I know that some FPGA support embedded 16 X 16 multiplier. However, is this operated in one clock cycle? Where can i get the layout/schematic/verilog design of this multiplier? Thanks

I've managed to get Lee Davison's EnhBASIC working on my 6502 SoC. (The hard part was getting the 6502 core to work properly.)...

I've managed to get Lee Davison's EnhBASIC working on my 6502 SoC. (The hard part was getting the 6502 core to work properly.) Lee's EnhBASIC was a snap to make use of. I've reduced the size of the core down to about 650 LUTs, so it should easily fit in a 10k device (although I h

Does anyone know of any work to impliment CPUs in PAL/GAL devices? Sort of a step between TTL & FPGA. Ken ...

Does anyone know of any work to impliment CPUs in PAL/GAL devices? Sort of a step between TTL & FPGA. Ken

Hi folks, I am a student designing an 8 bit cpu in an XCS10. I am using Visual HDL 6.7 and Xilinx ISE. Can someone tell me what...

Hi folks, I am a student designing an 8 bit cpu in an XCS10. I am using Visual HDL 6.7 and Xilinx ISE. Can someone tell me what is the method to link my cpu design to an internal ROM. By internal I mean a ROM made inside the Xilinx chip. I can use coregen to create the componen