regarding JTAG

Started by ponnmozhi in FPGA-CPU14 years ago 1 reply

hi, i am new to this field of fpga as such. could anyone give me any hint about using jtag to download design into fpga or any...

hi, i am new to this field of fpga as such. could anyone give me any hint about using jtag to download design into fpga or any information about jtag itself.(any links,websites etc..) plzz do help me out. thank you, pons


Re: RAM loading via JTAG

Started by Piotr Zbysinski - EP\\H\\ in FPGA-CPU13 years ago 6 replies

----- Original Message ----- From: Richard Duits To: lpc2000@lpc2... Sent: Thursday, August 18, 2005 1:15 AM Subject: Re:...

----- Original Message ----- From: Richard Duits To: lpc2000@lpc2... Sent: Thursday, August 18, 2005 1:15 AM Subject: Re: [lpc2000] RAM loading via JTAG When you switch the ARM7 into debug mode, all instructions and data are read from the jtag interface. You can just upload a ldm instruction for example with the data followin


JTAG

Started by gayatricontacts in FPGA-CPU14 years ago

hi, I am a new comer to this field of fpga(i.e i dont have any practical experience). I have started reading about boundary scan ...

hi, I am a new comer to this field of fpga(i.e i dont have any practical experience). I have started reading about boundary scan technique...could anyone please give website links etc which give the complete functioning and understanding of JTAG. Thank you, gayatri.


JTAG pins as I/O

Started by Guilherme Jorge in FPGA-CPU13 years ago 1 reply

Hi everyone How can i use the JTAG pins as I/O in my designs using Quartus II? Thanks

Hi everyone How can i use the JTAG pins as I/O in my designs using Quartus II? Thanks


Java JTAG API

Started by Kolja Sulimma in FPGA-CPU13 years ago 5 replies

I found the Java JTAG API that I was talking about. It is called JavaScan and has been withdrawn. ...

I found the Java JTAG API that I was talking about. It is called JavaScan and has been withdrawn. http://www.jcp.org/en/jsr/detail?id=2 (inkludes example source code to program a XC9500) There is a HAL that allows to efficien


Re: Low cost Altera board

Started by Martin Schoeberl in FPGA-CPU13 years ago 9 replies

> > I'm interested in the equivalence as well. My Z80 CP/M project > takes 2992 of the 6144 available LUTS in a XC2S300E Xilinx FPGA. ...

> > I'm interested in the equivalence as well. My Z80 CP/M project > takes 2992 of the 6144 available LUTS in a XC2S300E Xilinx FPGA. > The 'equivalent gate count' is 259,353 + 4704 for JTAG. I'm still > not clear about the definition of 'equivalent gate count' as it is > about 264k of the '300k' gate device, about 88%. On a LUT basis the


Parallel Port Programming Of Spartan IIE

Started by rtstofer in FPGA-CPU13 years ago 2 replies

Has anybody seen an app note that shows direct programming of a Spartan IIE from a PC parallel port without using iMPACT, JTAG or an ...

Has anybody seen an app note that shows direct programming of a Spartan IIE from a PC parallel port without using iMPACT, JTAG or an intermediate device such as a CPLD? I'm building another version of a logic analyzer with a 300k Spartan IIE and using the PC parallel port in EPP mode (bidirectional 8 bit with 6 control lines) rather than Centronics mod


FPGA to ARM7 shared memory concept via wishbone.

Started by djam...@gmail.com in FPGA-CPU8 years ago 5 replies

Hello Everyone. well i have designed a system that contains -- altera cyclone 3 FPGA, with 50M clock -- altera epcs16 Flash (configuration...

Hello Everyone. well i have designed a system that contains -- altera cyclone 3 FPGA, with 50M clock -- altera epcs16 Flash (configuration device for cyclone3) -- an LPC2468 ARM processor (running uLinux), -- a 16M Synchronous DRAM (connected to FPGA and ARM) -- rest the design has ethernet, usb memory device connector, FTDI interface, JTAG interface, ETXexpress Connector for connection to...