Software on Microblaze

Started by ramandeep_ahuja in FPGA-CPU15 years ago 1 reply

Hello, I am a newbie to FPGAs and Microblaze and need to write software that will run on the Microblaze - how hard would u say...

Hello, I am a newbie to FPGAs and Microblaze and need to write software that will run on the Microblaze - how hard would u say is development for the Microblaze? I prefer it over Power PC running Montavista for timing contraints .... do u agree ? Thanks in advan


doubt in configuration of cache in fpga

Started by ponnmozhi in FPGA-CPU14 years ago 4 replies

Hi, I am working on the spartanIIe FPGA and making use of the microblaze processor(EDK tool). My doubt is a very general one....

Hi, I am working on the spartanIIe FPGA and making use of the microblaze processor(EDK tool). My doubt is a very general one. basically the microblaze document says that cache in microblaze is implemented using Block RAM and on the other hand he also says that Block RAM can


Conectivity - Register, OPB,dip switch

Started by ramt...@... in FPGA-CPU13 years ago 1 reply

Hi I am looking for some help with the microblaze processor. I need to connect the registers on the microblaze processor to recieve input...

Hi I am looking for some help with the microblaze processor. I need to connect the registers on the microblaze processor to recieve input from the switches on the the board, on one hand and also connect to an opb peripheral at the other end. Has anyone done this? Thanks.


vga controller set as stdout.

Started by ponnmozhi in FPGA-CPU14 years ago 2 replies

Hi, I am using Xilinx Platform Studio with Microblaze as the processor and implementing the same on spartanIIE LC board.I am...

Hi, I am using Xilinx Platform Studio with Microblaze as the processor and implementing the same on spartanIIE LC board.I am able to use the uart alone as the STDIN and STDOUT. I have a user core (VGA controller) written & interfaced with the microblaze. I


Q, interconnections of microblaze

Started by jaeyoung_hur in FPGA-CPU13 years ago

hi all I want to preset the interconnection between microblazes (MB) For example of MESH interconnection, Consider 4...

hi all I want to preset the interconnection between microblazes (MB) For example of MESH interconnection, Consider 4 MBs. MB1 - MB2 - MB4, MB1 - MB3 - MB4 Could anyone guide me to preset this interconnection between microblaze I


Processor selection

Started by Avinash Shetty in FPGA-CPU15 years ago 3 replies

Hi Can any one let me know if there is any free open core for a 16 bit processor . I have studied the Picoblaze ....but its...

Hi Can any one let me know if there is any free open core for a 16 bit processor . I have studied the Picoblaze ....but its just 8 bits and the Microblaze is 32 bits ....both dont fit into what i am looking for ...something exactly like that which is 16bits ....cause all my interfacing


BRAM utilisation for CACHE.

Started by ponnmozhi in FPGA-CPU14 years ago 1 reply

hi, I am back with my cache problem. [this is implementing a design using the microblaze using EDK tool (xilinx Platform...

hi, I am back with my cache problem. [this is implementing a design using the microblaze using EDK tool (xilinx Platform Studio]. Since there are fixed possible sizes of BRAM which can be assigned,like for spartanIIe 2,4,8 KB First I tried executing with cache disabled-


Memory Management

Started by Rob Finch in FPGA-CPU13 years ago 3 replies

What kind of memory management features do the NIOS / Microblaze offer ? What would be appropriate for SoC systems ? I've...

What kind of memory management features do the NIOS / Microblaze offer ? What would be appropriate for SoC systems ? I've been working on a simple segmented system, plus a bitmap for execute / write able memory. But I'm thinking maybe I'm making things too complex. I


Xilinx vs Altera / Microblaze vs Nios???

Started by Mats Brorsson in FPGA-CPU14 years ago 14 replies

We are in the process of selecting an FPGA board for a series of laborations in courses ranging from computer engineering,...

We are in the process of selecting an FPGA board for a series of laborations in courses ranging from computer engineering, embedded software development to VHDL design, SoC architectures and operating systems. We are trying to evaluate Xilinx vs Altera boards


Re: Have NIOS and Microblaze killed off the fpga-cpu

Started by John Kent in FPGA-CPU12 years ago

Hi Hellwig, H...@mni.fh-giessen.de wrote: > > > > I've used a single phase clock on my designs. One clock cycle = one > > ...

Hi Hellwig, H...@mni.fh-giessen.de wrote: > > > > I've used a single phase clock on my designs. One clock cycle = one > > instruction cycle. > > That's really nice. How do you supply instructions > and operands from external memory with that rate? Your > machine has caches? Instructions and data separately There is no caching on the 6809 core. The address is set up was 35 ns


Question regarding FPGA (is this good enough?) and also the software needed

Started by asgf...@gmail.com in FPGA-CPU12 years ago 1 reply

I have previously worked on Spartan IIE boards while at Uni and am now wanting to continue tinkering with them at home to improve my skills. I...

I have previously worked on Spartan IIE boards while at Uni and am now wanting to continue tinkering with them at home to improve my skills. I came across the Spartan 3E Starter board at the Xilinx site for USD150 and am thinking of purchasing it. I intend to start off with some verilog to get me going again (basic stuff) and then I intend to eventually add a PicoBlaze or MicroBlaze or some stu...


(Q) interconnections of microblazes

Started by jaeyoung_hur in FPGA-CPU13 years ago

hi all I want to preset the interconnection between microblazes (MB) For example of MESH interconnection, Consider 4...

hi all I want to preset the interconnection between microblazes (MB) For example of MESH interconnection, Consider 4 MBs. MB1 - MB2 - MB4, MB1 - MB3 - MB4 Could anyone guide me to preset this interconnection between microblaze IP


To embed micontroller in FPGA ML401

Started by moraali_ali in FPGA-CPU11 years ago

Good morning I have a project where I need to embed microcontroller in a Xilinx ML401.This project consist a GSM which connect to a...

Good morning I have a project where I need to embed microcontroller in a Xilinx ML401.This project consist a GSM which connect to a microcontroller and the microcontrller is eventually connected to ML401.It is actually road traffic light implementation for Emergency Vehicle Preemption System. My friend told me that I could do this by implementing a Microblaze microprocessor i...


soft ip processors? history? advantages? vs ucontroller?

Started by umairsiddiqui0800 in FPGA-CPU14 years ago 2 replies

Sir, Soft IP Processors (my questions is from fpga prospective not from asic) have made strong hold in market, several...

Sir, Soft IP Processors (my questions is from fpga prospective not from asic) have made strong hold in market, several vendors like Xilinx(Picoblaze & Microblaze), @ltera(NIOS and NIOS-II) are making them. please do me a favor, I require some documents (articles


Microblaze In FPGA Virtex4 ML401?

Started by mora...@yahoo.com in FPGA-CPU11 years ago 13 replies

Good morning I have a project where I need to embed microcontroller in a Xilinx ML401.This project consist a GSM which connect to a...

Good morning I have a project where I need to embed microcontroller in a Xilinx ML401.This project consist a GSM which connect to a microcontroller(ATMEGA8535) and the microcontroller is eventually connected to Xilinx Virtex4 (ML401).It is actually road traffic light implementation for Emergency Vehicle Preemption System. My friend told me that I could do this by implementing a Microbl...