ModelSim/ISE4.1 problems for help

Started by wilton peter in FPGA-CPU16 years ago 2 replies

Dear All, I'm using ModelSim SE5.5f and ISE4.1i SP3 for my design. VHDL record types are used to define the entity ports. The...

Dear All, I'm using ModelSim SE5.5f and ISE4.1i SP3 for my design. VHDL record types are used to define the entity ports. The behavioral simulation works just well. But when I try post-translation/PAR simulation, it always reports: 'No default binding for component: "macrx". (Po


Question to ChipScope Pro users

Started by Jae Young Hur in FPGA-CPU13 years ago

Hi I need some comment from ChipScope Pro users, as I am new to ChipScope Pro VIO. I am using Xilinx ISE 6.3. Timing simulation after PAR...

Hi I need some comment from ChipScope Pro users, as I am new to ChipScope Pro VIO. I am using Xilinx ISE 6.3. Timing simulation after PAR (post place and route) simulation is okay. I exercised simple counter with ILA coregenerator. It works fine. Problem is the VIO. In ILA, proper behavior of the output signal can be seen. That is, the output signal behaves "0 -> 1