RISC Basic IS

Started by ~*Bushra Qamar*~ in FPGA-CPU10 years ago 7 replies

Hi, Im doing Bsc in electrical engineering....im in 7th semester....i'm doing work on RISC processor as the mini project....when i tried the...

Hi, Im doing Bsc in electrical engineering....im in 7th semester....i'm doing work on RISC processor as the mini project....when i tried the control unit and data path seperatley on fpga it runs well...but when i combined both...xilinx gives error"there is no processing in the design....Design in empty...."i could not understand how to solve this problem....can anay one plz help me..if ...


Xsoc 16bit RISC

Started by shibashish patel in FPGA-CPU14 years ago 3 replies

We were looking at the XSOC 16 bit RISC by Jan Gray. What is the role of the vga and can you explain its functioning. Can you explain...

We were looking at the XSOC 16 bit RISC by Jan Gray. What is the role of the vga and can you explain its functioning. Can you explain the test-bench written for the same. Yahoo! India Mobile: Ringtones, Wallpapers, Picture Messages and more.Download now.


I want to join any RISC processor design in Verilog HDL.

Started by Ben A. Abderazek in FPGA-CPU14 years ago 1 reply

Hello, Is there is any open CPU design project that I can join as a volunteer.? I can help designing a part of an open RISC...

Hello, Is there is any open CPU design project that I can join as a volunteer.? I can help designing a part of an open RISC processor in Verilog HDL. Regards, /Ben UEC, IS.


Started by steven_berbiers0 in FPGA-CPU14 years ago 3 replies

Hello there, My name is Steven Berbiers, I'm a Belgian college student. As a final work for next school year, me and a...

Hello there, My name is Steven Berbiers, I'm a Belgian college student. As a final work for next school year, me and a colleague have to build a tiny linux kernel for a FPGA machine. We have to synthesize a 32 bit RISC CPU which is capable of running this linux.


lisp machine anyone?

Started by Campbell, John in FPGA-CPU15 years ago 7 replies

Hi Has anyone considered building LISP machine? I know that RISC is the orthodox religion of the day, but it seems to me that ...

Hi Has anyone considered building LISP machine? I know that RISC is the orthodox religion of the day, but it seems to me that it might be fun to build a small LISP engine. The hardest part would be a garbage collector. Comments anyone? -jc


How to select an FPGA board

Started by Ben A. Abderazek in FPGA-CPU15 years ago 3 replies

Hello Helper, I want to implement a RISC-like processor on an FPGA board for education/research purpose. My question is...

Hello Helper, I want to implement a RISC-like processor on an FPGA board for education/research purpose. My question is what is the suitable board I should buy? And how much it costs? Thank you for your help, BEN ABDERAZEK University of E


vliw code

Started by Bushra Qamar in FPGA-CPU10 years ago 1 reply

Hi I'm Bushi..doing electrical engineering from u.e.t. Taxila,Pakistan i was doing final year project on vliw my project advisor said me to...

Hi I'm Bushi..doing electrical engineering from u.e.t. Taxila,Pakistan i was doing final year project on vliw my project advisor said me to implement 8-bit risc i did then he said me to design 32 bit mips i did =A0 now he is not telling me what to do=20 he has gone to norway and i have to submit my project on 16th of august i couldnot understand what to do next and how:( he did'nt tell...


small CPUs

Started by Jan Gray in FPGA-CPU14 years ago 3 replies

> The XSOC RISC is also not very small. That stings! Oh well -- de gustibus non disputandem est -- so what's new in small...

> The XSOC RISC is also not very small. That stings! Oh well -- de gustibus non disputandem est -- so what's new in small processor cores? Anyone care to fill in the table below with more recent entries? Small (IMHO): PicoBlaze: 76-96 slices (approx. double to


difference between these two books

Started by Srinath Bagal V in FPGA-CPU15 years ago 2 replies

Hello Group, I wanted to know the difference between these two books. Which is more helpful for a hardware student willing to...

Hello Group, I wanted to know the difference between these two books. Which is more helpful for a hardware student willing to build a small RISC? Computer Organization and Design: The Hardware/Software Interface by David A. Patterson, John L. Hennessy, Nitin Indurkhya


8-bit microprocessor

Started by ashfaq_bse in FPGA-CPU11 years ago 6 replies

hey people hop all of u ppl will b fine. i m a student of B.Sc. Computer engineering. i m going to make a degree project of "8-bit...

hey people hop all of u ppl will b fine. i m a student of B.Sc. Computer engineering. i m going to make a degree project of "8-bit microprocessor based on MIPS architecture (RISC) implemented on verilog and synthesized oin FPGA" if any one have this project he/she should help me out so that i could vast ma project scope. i shall b really grateful to u ppl. thanking u ppl in anticipa...


Execution unit in Verilog ?

Started by Ben A. Abderazek in FPGA-CPU14 years ago 3 replies

Dear helper, I am implementing a new processor in verilog. I am no near the execution unit implementation!! Does any one have...

Dear helper, I am implementing a new processor in verilog. I am no near the execution unit implementation!! Does any one have (or know) a full design of RISC-style instructions execution unit in verilog. I am planning to implement 1 ALU unit, 1 Branch unit, 1 SET unit, and 1


few questions related to 16-bit cpu core design

Started by umairsiddiqui0800 in FPGA-CPU14 years ago 8 replies

I'm ee student, I want to built 16-bit cpu core for final-year project. for core, I have been studying x86 and RISC arch(s) and...

I'm ee student, I want to built 16-bit cpu core for final-year project. for core, I have been studying x86 and RISC arch(s) and cores (as completely cheating instructor is not possible!!!). In addition my instructor is saying that I have demontrate the cpu by implementing


ANN: Introducing MANIK - a 32 bit Soft-Core RISC Processor

Started by sandeep94404 in FPGA-CPU14 years ago 1 reply

http://www.niktech.com Hardware Features ? Data Path Width 32 bits ? Most instructions are 16 bit. PC Relative...

http://www.niktech.com Hardware Features ? Data Path Width 32 bits ? Most instructions are 16 bit. PC Relative jump instructions are 32 bit. ? Four stage pipeline. ? Von Neumann Architecture (Data and Instr


Dose Altera Nios support hardware-based multi-thread and how?

Started by qfmyue in FPGA-CPU14 years ago 1 reply

In Altera development kits ,I can't find the description about it. The Nios(tm) CPU soft core is a 16/32-bit RISC CPU...

In Altera development kits ,I can't find the description about it. The Nios(tm) CPU soft core is a 16/32-bit RISC CPU core,specially, it has the sliding register file windows technology. So I think it maybe support hardware multi-thread technology,but I can't find the relatial ma


Good FPGA developmnet Board

Started by Ben A. Abderazek in FPGA-CPU15 years ago 1 reply

Hello helpers, I need to buy an FPGA to implement a 32-bit RISC-like processor. I found this board: APEX PCI Development Kit...

Hello helpers, I need to buy an FPGA to implement a 32-bit RISC-like processor. I found this board: APEX PCI Development Kit (APEX 20KE) from Altera ( http://www.altera.com/produc ts/devkits/kit-dev_platforms.jsp