Calling a verilog-like package from VHDL

Started by shaik afzal in FPGA-CPU15 years ago 1 reply

Hi all, Hope this is not an off-topic query. We have a set of VHDL Design files(Say VHDL1.Vhd,VHDL2.vhd etc.) and a VHDL...

Hi all, Hope this is not an off-topic query. We have a set of VHDL Design files(Say VHDL1.Vhd,VHDL2.vhd etc.) and a VHDL Package(VHDL_pack.vhd) file. VHDL Design files(VHDL1.Vhd,VHDL2.vhd etc) and VHDL Package (VHDL_pack.vhd) file is converted to equivalent


CISC architecture processor in vhdl & then in fpga (LeonardoSpectrum - ModelSim)

Started by xrisas1 in FPGA-CPU13 years ago 1 reply

I'm a student.I'm now learning VHDL. Help. I'm looking for a generic vhdl library. Registers,ALU,Shifter,RAM,SubSequencer. ...

I'm a student.I'm now learning VHDL. Help. I'm looking for a generic vhdl library. Registers,ALU,Shifter,RAM,SubSequencer. HELP. Implementing CISC architecture processor in Book : Computer Designs Funtamentals, Morris Mano HELP


verilog to vhdl

Started by eesha_78 in FPGA-CPU15 years ago 3 replies

i'm very new in this area. i want to know how to convert from verilog to vhdl language..for example assign a= &b[7:0]; ...

i'm very new in this area. i want to know how to convert from verilog to vhdl language..for example assign a= &b[7:0]; assign c= |d[7:0]; when i try to convert to vhdl.. a= and b(7 downto 0); c or d(7 downto 0); but there was an erro


How Input & OutputFile Use in testbench in VHDL!

Started by nastaran mmmmm in FPGA-CPU14 years ago 1 reply

How can I use of Inputfile & Outputfile(TEXTIO) in testbench in VHDL. I download and study all of documents from internet. ...

How can I use of Inputfile & Outputfile(TEXTIO) in testbench in VHDL. I download and study all of documents from internet. Thus, I need a sample program that include main modul and its testbench in VHDL. I have foundation ISE Thank you ---------


Design mini cpu?

Started by potxoka3a in FPGA-CPU9 years ago 5 replies

hi I=C2=B4m new to VHDL and FPGA. I=C2=B4m currently doing a design in an FPGA= with VHDL, analyzing and changing a few signs of a data bus...

hi I=C2=B4m new to VHDL and FPGA. I=C2=B4m currently doing a design in an FPGA= with VHDL, analyzing and changing a few signs of a data bus of 20 signals = (transceiver). These signals often change protocol, as the team changes dur= ing the design in VHDL I changed 2 times. To avoid having to always fpga programming, thought if there was any way to= change the interpretation of these s...


VHDL and Verilog

Started by Jin Yan in FPGA-CPU15 years ago 4 replies

Hi, everyone, I am new in this field. Could somebody kindly tell me which one, VHDL or Verilog, is commonly used in industry?...

Hi, everyone, I am new in this field. Could somebody kindly tell me which one, VHDL or Verilog, is commonly used in industry? Or which language is suitable to what kind of application? I am choosing one language to do fpga programming and wondering the pros


SLL in VHDL

Started by Frangline Jose in FPGA-CPU16 years ago 2 replies

Hi, I tried to use SLL, ROR ... in VHDL. Iam using modelsim for simulation, Here is the command I used, vcom -93...

Hi, I tried to use SLL, ROR ... in VHDL. Iam using modelsim for simulation, Here is the command I used, vcom -93 shifter.vhd My code is, LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.Numeric_STD.all; ENTITY


DWT in vhdl

Started by siva...@gmail.com in FPGA-CPU10 years ago 3 replies

hi, how to implement discrete wavelet transform for image compression in vhdl.plz. give me brief idea. if anyone has source code please send...

hi, how to implement discrete wavelet transform for image compression in vhdl.plz. give me brief idea. if anyone has source code please send to me. thank you To post a message, send it to: f...@yahoogroups.com To unsubscribe, send a blank message to: f...@yahoogroups.com


Re: VHDL and Verilog... the answer?

Started by in FPGA-CPU15 years ago 3 replies

Hi everybody!!!! This is an interesting controversy. Some month ago I was looking for an answer to the question: "what is...

Hi everybody!!!! This is an interesting controversy. Some month ago I was looking for an answer to the question: "what is better: Verilog or VHDL?". But really I have not found a conclusive answer. why?, Each languages has advantages and disadvantages. However


Need Frequency Demodulation VHDL Source

Started by shahram ghaebi in FPGA-CPU15 years ago 1 reply

Dear Friends I need Need Frequency Demodulation VHDL Source can you help me? Regards __________________________________ ...

Dear Friends I need Need Frequency Demodulation VHDL Source can you help me? Regards __________________________________


TO_UNSIGNED command in vhdl

Started by siva...@gmail.com in FPGA-CPU10 years ago 1 reply

hi, any one please tell me, the use of commands TO_UNSIGNED, TO_INTEGER,TO_SIGNED in vhdl language. To post a message, send it to:...

hi, any one please tell me, the use of commands TO_UNSIGNED, TO_INTEGER,TO_SIGNED in vhdl language. To post a message, send it to: f...@yahoogroups.com To unsubscribe, send a blank message to: f...@yahoogroups.com


how to declare global variables in a package

Started by gupta ksrc in FPGA-CPU15 years ago

hi everybody i have some small problem related vhdl programming. I have to convert C code to vhdl code on xilinx platform. ...

hi everybody i have some small problem related vhdl programming. I have to convert C code to vhdl code on xilinx platform. In the c code one program consisting of all functions and in that begining of program they declared "overflow" and "carry" as


AHDL Convertor

Started by hadi khani in FPGA-CPU15 years ago 4 replies

Hi, I have old codes in AHDL, I am going to my codes to VHDL and I do not have sufficient time for rewriting. Does any body know an AHDL to...

Hi, I have old codes in AHDL, I am going to my codes to VHDL and I do not have sufficient time for rewriting. Does any body know an AHDL to VHDL convertor. thanks


Need Digital Low Pass Filter Vhdl source

Started by shahram ghaebi in FPGA-CPU14 years ago 2 replies

I need optimized Digital Low Pass Filter vhdl source. can you help me? regards __________________________________ ...

I need optimized Digital Low Pass Filter vhdl source. can you help me? regards __________________________________


vhdl design of 8 bit processor

Started by varadaprasad1 in FPGA-CPU9 years ago 2 replies

I need VHDL design for 8 bit processor,which is part of my project.Please mail me the codes or the link for the code,if any one of you have the...

I need VHDL design for 8 bit processor,which is part of my project.Please mail me the codes or the link for the code,if any one of you have the same. ------------------------------------ To post a message, send it to: f...@yahoogroups.com To unsubscribe, send a blank message to: f...@yahoogroups.com


Sorting in VHDL

Started by Sumeet Suri in FPGA-CPU16 years ago 4 replies

Hey Guys, I wanted to implement sorting of 255 numbers which are 32 bit each. Sorting of 2, 1 bit numbers is a easy thing. but...

Hey Guys, I wanted to implement sorting of 255 numbers which are 32 bit each. Sorting of 2, 1 bit numbers is a easy thing. but with such large numbers will it be easy to implement it in VHDL. Have any of you guys tried doing this? Sumeet


anyone has ps2 keyboard controller cores?

Started by cationebox in FPGA-CPU13 years ago 2 replies

can anyone help me ? i will use it in my project but i am not sure to write right code in time so i turn to you can you help me...

can anyone help me ? i will use it in my project but i am not sure to write right code in time so i turn to you can you help me ? vhdl is better than in verilog thanks a lot


sdf simulations

Started by Rahul Vishal in FPGA-CPU13 years ago

Hi everyone, I am trying to do a post layout simulation. One that is done after the PnR is over. I have got the Vhdl netlist and also...

Hi everyone, I am trying to do a post layout simulation. One that is done after the PnR is over. I have got the Vhdl netlist and also the sdf file. But the NClaunch gives me all kinds of warnings like : Component Instance not fully bound and so on. Is there any place I can look for a solution? Can anybody help me ??? Bye Ra


ADC

Started by sukumar in FPGA-CPU13 years ago 4 replies

Hi all, I am using Altera Quartus II ver4.0 tool - VHDL langauage. Please any body guide me how to do ADC with/without...

Hi all, I am using Altera Quartus II ver4.0 tool - VHDL langauage. Please any body guide me how to do ADC with/without using analog related library..? Thank you, --sukumar


Intel 8088

Started by Mogens Pelle in FPGA-CPU14 years ago 1 reply

Hi there Does anybody here know about a 8088-compatibel core written in VHDL? Regards Mogens Pelle Engineering College of...

Hi there Does anybody here know about a 8088-compatibel core written in VHDL? Regards Mogens Pelle Engineering College of Copenhagen