Execution unit in Verilog ?

Started by Ben A. Abderazek in FPGA-CPU13 years ago 3 replies

Dear helper, I am implementing a new processor in verilog. I am no near the execution unit implementation!! Does any one have...

Dear helper, I am implementing a new processor in verilog. I am no near the execution unit implementation!! Does any one have (or know) a full design of RISC-style instructions execution unit in verilog. I am planning to implement 1 ALU unit, 1 Branch unit, 1 SET unit, and 1


x86 16bit CPU

Started by N S in FPGA-CPU11 years ago

One of my graduated student agreed to open his design under the GPL. I put the sample code "x86FPGA package" under my...

One of my graduated student agreed to open his design under the GPL. I put the sample code "x86FPGA package" under my web. http://www.ip-arch.jp/indexe.html It requires: sfl2vl (convert SFL to Verilog), Icarus Verilog, NASM and some other UNIX tools to run simulation. We have ran FreeDOS under Icarus Verilog, and also we ran a monitor program on ALTERA UP3 FPGA board. maybe I s...


How design a FIFO in Verilog?

Started by xvibe in FPGA-CPU15 years ago 1 reply

Can you explain me how to design a FIFO in Verilog? The FIFO that I'm talking about is of this type: ...

Can you explain me how to design a FIFO in Verilog? The FIFO that I'm talking about is of this type: ------------------------------- | | ---| DataIN DataOUT |--- | | ---| WR# RD# |--- | | ---|> CLKIN CLKOUT <|--- | | ----


VHDL and Verilog

Started by Jin Yan in FPGA-CPU15 years ago 4 replies

Hi, everyone, I am new in this field. Could somebody kindly tell me which one, VHDL or Verilog, is commonly used in industry?...

Hi, everyone, I am new in this field. Could somebody kindly tell me which one, VHDL or Verilog, is commonly used in industry? Or which language is suitable to what kind of application? I am choosing one language to do fpga programming and wondering the pros


OT: verilog arrays

Started by Rob Finch in FPGA-CPU13 years ago 2 replies

Does anyone know how to pass arrays to a module in Verilog ? I tried this as a test but it doesn't work: module...

Does anyone know how to pass arrays to a module in Verilog ? I tried this as a test but it doesn't work: module arrayTest(s, a, o); input [2:0] s; input [3:0] a [4:0]; // this line cause the synthesizer to croak with an error 'expecting ; not [ ' output [3


FW: Verilog simulator

Started by J O in FPGA-CPU11 years ago 1 reply

Hello I want to continue exploration of cpu archtectures in my past time and wondered if anyone knew of a low cost verilog simulator that i...

Hello I want to continue exploration of cpu archtectures in my past time and wondered if anyone knew of a low cost verilog simulator that i could purchase for home use ? Thanks J.Osmany _________________________________________________________________ Windows Live? Messenger has arrived. Click here to download it for free! http://imagine-msn.com/messenger/launch80/?locale=en-gb ...


Re: VHDL and Verilog... the answer?

Started by in FPGA-CPU15 years ago 3 replies

Hi everybody!!!! This is an interesting controversy. Some month ago I was looking for an answer to the question: "what is...

Hi everybody!!!! This is an interesting controversy. Some month ago I was looking for an answer to the question: "what is better: Verilog or VHDL?". But really I have not found a conclusive answer. why?, Each languages has advantages and disadvantages. However


Verilog code for an *bit Microprocessor

Started by junaid_id1981 in FPGA-CPU15 years ago 1 reply

I am searching for verilog code for an 8-bit cpu. I'm trying to design my own 8 bit cpu with about 32-64 instructions based on...

I am searching for verilog code for an 8-bit cpu. I'm trying to design my own 8 bit cpu with about 32-64 instructions based on 8085 cpu. Urgent help is warrented. Thanks


verilog to vhdl

Started by eesha_78 in FPGA-CPU15 years ago 3 replies

i'm very new in this area. i want to know how to convert from verilog to vhdl language..for example assign a= &b[7:0]; ...

i'm very new in this area. i want to know how to convert from verilog to vhdl language..for example assign a= &b[7:0]; assign c= |d[7:0]; when i try to convert to vhdl.. a= and b(7 downto 0); c or d(7 downto 0); but there was an erro


fpgasm - a low-level design language for Xilinx FPGAs

Started by "arm7.developer" in FPGA-CPU5 years ago

Hello, I would like to present to you an alternative to Verilog and VHDL - FPGA Assembler. I've been fiddling with FPGAs for a while. ...

Hello, I would like to present to you an alternative to Verilog and VHDL - FPGA Assembler. I've been fiddling with FPGAs for a while. I've been working on some open source tools to make FPGA work not totally unpleasant. fpgasm is to Verilog is what assembly language is to C++. With fewer than 10 reserved words, you can actually start hacking in minutes. Anyway, I hope you get a chanc...


I want to join any RISC processor design in Verilog HDL.

Started by Ben A. Abderazek in FPGA-CPU14 years ago 1 reply

Hello, Is there is any open CPU design project that I can join as a volunteer.? I can help designing a part of an open RISC...

Hello, Is there is any open CPU design project that I can join as a volunteer.? I can help designing a part of an open RISC processor in Verilog HDL. Regards, /Ben UEC, IS.


Implementation of LRU algo in verilog

Started by ruchi_rastogi25 in FPGA-CPU8 years ago 6 replies

Hi all, I am designing a cache memory in verilog. I am facing problem in desiging LRU unit for set associative cache. Can anybody tell me what is...

Hi all, I am designing a cache memory in verilog. I am facing problem in desiging LRU unit for set associative cache. Can anybody tell me what is the optimal way of implementating LRU(Least Recently Used)algo in Hardware. Thanks, Ruchi ------------------------------------ To post a message, send it to: f...@yahoogroups.com To unsubscribe, send a blank message to: f...@yahoogroups.com ...


Re: Alpha or Alpha-like processor Verilog code

Started by h_zarandi in FPGA-CPU8 years ago

Dear Ben, Do you have HDL source code of Alpha processor? /hamid --- In f...@yahoogroups.com, "Ben A. Abderazek" wrote: > > Hello...

Dear Ben, Do you have HDL source code of Alpha processor? /hamid --- In f...@yahoogroups.com, "Ben A. Abderazek" wrote: > > Hello Helpers, > > Does any one have or know a Verilog source code of Alpha 21164 (or > Alpha -like) processor?. > Many thanks for your help, > > /Ben > UEC, IS, Japan > ------------------------------------ To post a message, send it to: f..


anyone has ps2 keyboard controller cores?

Started by cationebox in FPGA-CPU13 years ago 2 replies

can anyone help me ? i will use it in my project but i am not sure to write right code in time so i turn to you can you help me...

can anyone help me ? i will use it in my project but i am not sure to write right code in time so i turn to you can you help me ? vhdl is better than in verilog thanks a lot


interconnection between FPGA and PC

Started by RANJITH KUMAR REDDY in FPGA-CPU10 years ago 5 replies

Hello Can any one help me regarding how to connect the FPGA to a micro processor simulator. I am actually trying to do a project...

Hello Can any one help me regarding how to connect the FPGA to a micro processor simulator. I am actually trying to do a project on Using FPGA to implement Floating point multiplier were the FPGA does the required multiplication for microprocessor to speed up, for which i am writing a Verilog code and dump it into FPGA now i want to simulate it and see the performance. I j...


Re: Sydney-X1 FPGA Computer Challenges Commodore

Started by fpgauser in FPGA-CPU13 years ago

Hi Tony B, I have just read your post. I want to know if the board comes with the vhdl or verilog or IP cores to get the...

Hi Tony B, I have just read your post. I want to know if the board comes with the vhdl or verilog or IP cores to get the demos working, as avertised and shown on your web site? Is that what the restricted area is for, to download these files etc.


Re: Question about the STACK size: + Instruction Register

Started by Ben A. Abderazek in FPGA-CPU14 years ago

Thank you Towas for the details. I understand it very well and I implement a hardware stack as a first implementation. I do...

Thank you Towas for the details. I understand it very well and I implement a hardware stack as a first implementation. I do not have so much experience in processor and verilog HDL design that is why I am asking probably very basic question for you. I have another quest


Logic Number from Net lists

Started by Ben A. Abderazek in FPGA-CPU14 years ago

Hi, I am using FPGA compiler II to generate net list of a Verilog module. The module can be compiled without any error and I can...

Hi, I am using FPGA compiler II to generate net list of a Verilog module. The module can be compiled without any error and I can find the Est. Frequency from the optimized chips. I want to know is it possible to know also the number of gates? If it is not possible, is there are any


Help - Shifter using MUXCYs

Started by Lucian Damoc in FPGA-CPU13 years ago 8 replies

Hello, I've designed a shifter using only MUXCYs (found in Xilinx FPGAs). Instead of using the usual 2:1 MUX (implemented in a...

Hello, I've designed a shifter using only MUXCYs (found in Xilinx FPGAs). Instead of using the usual 2:1 MUX (implemented in a LUT), I've used the MUXCY (see the attached Verilog file). XST synthesized the design with no errors/warnings (target device = SpartanIIE, 300K). The delay (as shown in the .syr file) seems very good.


Pipelined Processor and Buffers

Started by Ben A. Abderazek in FPGA-CPU13 years ago 10 replies

Dear Helpers, I am implementing an FPGA pipelined processor that is expected to fetch and execute 2 inst/cycle. I want to...

Dear Helpers, I am implementing an FPGA pipelined processor that is expected to fetch and execute 2 inst/cycle. I want to implement buffers to separate each stage/unit. Since I am not so familiar with HDL (Verilog), I want to know (probably) a very basic question