BRAM speed [was: Multi-context processor]

Started by Tommy Thorn in FPGA-CPU12 years ago

I just started playing with Xilinx Spartan 3E (speed grade -4) and I was appalled to find that even with extreme care can I only run the BRAMs at...

I just started playing with Xilinx Spartan 3E (speed grade -4) and I was appalled to find that even with extreme care can I only run the BRAMs at 170 MHz. Anything realistic and the speed drops much further. This is compared to my age-old Altera Cyclone which happily ran north of 200 MHz. You'd need X and A's performance parts (Virtex/Stratix) to get anywhere near 300 MHz. Xilinx Virtex 5 claim...


Power optimization at Code level?

Started by gutty19 in FPGA-CPU13 years ago 1 reply

Hi, I am concerend more on Virtex fpgas. Are there any special way of planning the architecture of a fpga design which would reduce...

Hi, I am concerend more on Virtex fpgas. Are there any special way of planning the architecture of a fpga design which would reduce the power consumption (for eg. reducing operating frequency etc.). If there is some paper/resource available on these tips, it would be really helpful. Thanks, gutty.


Re: Digest Number 512

Started by Sagar Sen in FPGA-CPU15 years ago

Hi Gian try the virtex 1 or 2 memory rich architecture. Sagar On Sun, 06 Jul 2003 wrote : >To post a message, send it...

Hi Gian try the virtex 1 or 2 memory rich architecture. Sagar On Sun, 06 Jul 2003 wrote : >To post a message, send it to: >To unsubscribe, send a blank message to: > >----------------------------------------------------------------------


Transputers [ was What are peoples opinion of the Altera Nios Processor? ]

Started by John Kent in FPGA-CPU15 years ago 5 replies

Hi Josh, I'd be interested to see your paper when you are finished. The Leon looks nice ... but I don't have a 800K gate...

Hi Josh, I'd be interested to see your paper when you are finished. The Leon looks nice ... but I don't have a 800K gate Virtex FPGA to play with. I'm using the BurchED FPGA board with the XC2S200. Are there any small 32 bit CPUs that will fit in a 200K gate FPGA ?


Re: BGA prototyping

Started by Ed Corter in FPGA-CPU14 years ago 7 replies

Here are 2 pic's of my prototype that uses a xilinx virtex 300 BGA 350 somthing (lots) pic 1 shows the IO VCC, Core VCC and the...

Here are 2 pic's of my prototype that uses a xilinx virtex 300 BGA 350 somthing (lots) pic 1 shows the IO VCC, Core VCC and the ground rings and the bypassing capacitors used. the pic doesnt show the 2 switching regulators built on board.


help - creating macros

Started by harish in FPGA-CPU12 years ago 1 reply

Hi guys, i have a small query. i have a small design and i have to place this design and compact it to the left most corner of the FPGA. i...

Hi guys, i have a small query. i have a small design and i have to place this design and compact it to the left most corner of the FPGA. i did this using the FPGA Editor, by manually placing and routing the whole design. BTW, i am using a virtex II fpga, (XC2v1000). then i created a macro by saving the file as a (*.nmc). now i have to place this macro at the right hand most corner of ...


FPGA DIMM module

Started by John Pham in FPGA-CPU15 years ago 1 reply

Hello, I like to introduce our FPGA DIMM module for development/Prototype work The unit use Xilinx Virtex FPGA (XCV50 to XCV600)...

Hello, I like to introduce our FPGA DIMM module for development/Prototype work The unit use Xilinx Virtex FPGA (XCV50 to XCV600) with ethernet+flash+ram+CPLD. please visit my site at http://snaplogix.tripod.com for more informat


Inquiry about FPGA and PowerPC codesign

Started by in FPGA-CPU11 years ago

Hi all I am working on Xilinx ML310, with VirtexII pro fpga on it. Now I am trying to make the FPGA and PowerPC cores(embedded in VirtexII...

Hi all I am working on Xilinx ML310, with VirtexII pro fpga on it. Now I am trying to make the FPGA and PowerPC cores(embedded in VirtexII Pro) co-work. For example, build a filter in verilog HDL in FPGA, and set up PPC to do some control work and other data processing. After following the manual from xilinx (EDK 7.1 PowerPC Tutorial in Virtex-4) and download the bit to FPGA, I got nothi...