Disable RX on UARTS

Started by extra300_it in LPC200013 years ago 1 reply

Hello, I have an external circuit that echoes back the caracters that I am sending out of UARTs. Is there any way to disable RX while...

Hello, I have an external circuit that echoes back the caracters that I am sending out of UARTs. Is there any way to disable RX while I'm transmitting (like Rx Enable on other micros)? -I am using FIFO- I disabled both RX interrupts during transmission. When tx is ended, I clear FIFO buffers (UxFCR bit 1) This should clear


Strange behavior on P0.02/P0.03

Started by Curt Powell in LPC200013 years ago 2 replies

We're seeing some strange pin behavior between an lpc2106 (on an Olimex H2106 board) and a USB FIFO (DLPUSB245M). I'm wondering if...

We're seeing some strange pin behavior between an lpc2106 (on an Olimex H2106 board) and a USB FIFO (DLPUSB245M). I'm wondering if anyone has any ideas. When running a simple loopback test sending data from lpc to FIFO, bits 2 and 3 (on P0.02 and P0.03) do not get set to 1 but on the


UART Status Question

Started by Bill Wittig in LPC200012 years ago 1 reply

Hi, In reading the User Manual (for the LPC213x), I'm unclear on the meaning of the THRE bit in the LSR: Does this mean the entire Tx FIFO...

Hi, In reading the User Manual (for the LPC213x), I'm unclear on the meaning of the THRE bit in the LSR: Does this mean the entire Tx FIFO is empty? That is, I can write 16 bytes to it whenever LSR:THRE is set? Or, does it just mean that there's at least one byte of space available in the FIFO? Any experience / clarification is greatly appreciated! bill


Filling SSP fifo after GPDMA transfer

Started by Kuba Dorzak in LPC20006 years ago 1 reply

Hi Everybody, what I am trying to do is: 1) fill fifo at slave side using CPU 2) init GPDMA for SSP slave transfer 3) wait for master to...

Hi Everybody, what I am trying to do is: 1) fill fifo at slave side using CPU 2) init GPDMA for SSP slave transfer 3) wait for master to start transfer 5) when transfers from master and slave are finished I block at slave side GPDMA channels and reload fifo (using CPU) and wait for master to send next package. This way I expect to have valid data at master side- because I fill the fif...


lpc2148: wiered SSP behaviour or hardware bug???

Started by diwilru in LPC200012 years ago 1 reply

Hi Fellows, Something strange happens when I try to use SSP in lpc2148. So, I initiate SSP as per spi1_init(2,11) in SPI mode with tx...

Hi Fellows, Something strange happens when I try to use SSP in lpc2148. So, I initiate SSP as per spi1_init(2,11) in SPI mode with tx FIFO half empty interrupts enabled (see the code below). Then I start to transfer bytes over SPI. The first portion of the data until tx FIFO is empty being transfered Ok. Then I expect SPI1 interrupt


DMA read from MCI fifo

Started by Kuba Dorzak in LPC20006 years ago 13 replies

Hi everybody, I am trying to use DMA transfer to get MCI fifo data. I used Juri Haberland's driver, which works perfectly with 1-bit SDbus...

Hi everybody, I am trying to use DMA transfer to get MCI fifo data. I used Juri Haberland's driver, which works perfectly with 1-bit SDbus without DMA. I can write data to MCI using the GPDMA, but reading fails. My question concerns DMA configuration: 1) firstly, I am setting DMA source, destination and channel 1 control: [code] else if (mode == dmaP2M) { ...


How Erase LPC2129-UART RX FIFO

Started by srk in LPC200011 years ago 1 reply

Hi The code written for rx data in LPC2129-uartO U0LCR = 0x83; U0DLL = 39; // baud rate = 9615 ...

Hi The code written for rx data in LPC2129-uartO U0LCR = 0x83; U0DLL = 39; // baud rate = 9615 @ pclk = 6mhz U0FCR = 0x07; //FIFO enable U0LCR = 0x03; //Rx data as 8 bits, no Parity, 1 Stop bit while(!(U0LSR & 0x01)); //executed untill U0RSR full while(U0LSR & 0x01) { ch3[x] = U0R...


UART Test w/ Blinky Lights - Updated

Started by Bill Knight in LPC200013 years ago

Based upon the recent discussions concerning the UART TX FIFO, I have updated my UART Test w/ Blinky Lights program in the files section....

Based upon the recent discussions concerning the UART TX FIFO, I have updated my UART Test w/ Blinky Lights program in the files section. The new (totally undescriptive) name is UT050418A.zip. The ISR code now checks if the FIFO is enabled when servicing a THRE interrupt. If so, 16 characters are loaded into the UART. If not, only a single character is load


LPC2119 How to block or disable interrupts momentarily

Started by "alastair.stell" in LPC20008 years ago 2 replies

Newbie unfortunately. I need to pass data received from a CANbus interrupt interrupt to the application (note I am not using an RTOS at...

Newbie unfortunately. I need to pass data received from a CANbus interrupt interrupt to the application (note I am not using an RTOS at present). I am looking for a safe way to pass data acquired by the interrupt into the application. I was hoping to use a simple fifo queue mechanism but I am concerned the application and interrupt might collide while accessing the fifo queue. So I was cons...


can't get uart tx fifo to work

Started by fhriley in LPC20006 years ago 12 replies

Hello, I've got my uart code working fine, however, when measuring it with a scope, it appears the TX fifo is not working. I send a byte with...

Hello, I've got my uart code working fine, however, when measuring it with a scope, it appears the TX fifo is not working. I send a byte with the following code: while ((LPC_UART-> LSR & LSR_THRE) == 0); LPC_UART-> THR = ch; I call this in a loop to send the message. I would expect this loop to be fast for the first 16 bytes, however I see the first byte take 830ns, the second 2.2us, and t


C open source extension library

Started by Felipe de Andrade Neves Lavratti in LPC20004 years ago 3 replies

Folks, I ended up building a library with common stuff (Fifos, stacks, etc.) that I use in embedded systems and uploaded it to the github....

Folks, I ended up building a library with common stuff (Fifos, stacks, etc.) that I use in embedded systems and uploaded it to the github. It's called chelper. Here are the modules that chelper already implements: Vector Ring FIFO Fast Ring FIFO String Signal Slot with no argument Signal Slot with two int arguments Signal Slot with data argument (void * ...


Detecting multiple key presses

Started by ajellisuk in LPC200010 years ago 1 reply

Hi I have a project were I'm using an LPC2148, and a MAX7349 for the keypad interface. The MAX7349 has a FIFO register for storing key press...

Hi I have a project were I'm using an LPC2148, and a MAX7349 for the keypad interface. The MAX7349 has a FIFO register for storing key press events. I need to be able to detect simultainious key presses. I have noticed that when I press two keys together a sperate key press event is stored in the FIFO register ie 1 event for each of the keys pressed together. Could someone please ...


LPC214x: Can we really manage the SSP (SPI mode) in interrupt mode????

Started by croquettegnu in LPC200011 years ago 2 replies

Hi All, I'm really confused on how to deal with the SSP interrupts to manage my SPI transfers. There are two flags called RXIM and TXIM that...

Hi All, I'm really confused on how to deal with the SSP interrupts to manage my SPI transfers. There are two flags called RXIM and TXIM that allows to trig an interrupt as soon as the TX FIFO is half empty and the Rx FIFO is half full. These are the only flags that can be used to generate an interrupt (except error flags). But I do NOT understand how to manage my transfer with such inter...


LPC2138 RX FIFO (not)

Started by Lowry, Jeff in LPC200013 years ago

Can't seem to get the RX FIFO on UART0 to work... My setup: U0IER bit 0 =1, Enabled RDA interrupt (receive data interrupt) U0IER...

Can't seem to get the RX FIFO on UART0 to work... My setup: U0IER bit 0 =1, Enabled RDA interrupt (receive data interrupt) U0IER bit 1 = 1, Enable THRE enterrupt (transmit data interrupt) U0IER bit 2 = 1, Enabled the Rx line status interrupts U0FCR bit 0 = 1, Enabled both RX and TX FIFOs U0FCR bit 7:6 = 3, Rx trigger level of 14 chars


LPC2888

Started by beds_dave in LPC200010 years ago

Hi, Does anyone know if the bug about running thumb code in flash and also the MCI fifo bug has been cured and in what mask version or date...

Hi, Does anyone know if the bug about running thumb code in flash and also the MCI fifo bug has been cured and in what mask version or date code cpu chip it works ok ? I have a 'Y' mask version made in week 36 of 2007 and thumb code doesnt work in this. The errata sheet only mentions mask version '-'. The MCI fifo bug is supposed to be cured in parts 01 & D1 mentioned in the latest ...


LPC2104 UART0 FIFO problem

Started by yxh510 in LPC200013 years ago

HI, When I using UART0 FIFO for receive 4 byte interrupt.the problem is: It can only receive 3 byte then go interrupt.When I send 4 byte...

HI, When I using UART0 FIFO for receive 4 byte interrupt.the problem is: It can only receive 3 byte then go interrupt.When I send 4 byte from PC to LPC2104 It go breakdown and can't work.Why? Does anyone know ,tahnk you!


LPC2478: SD card DMA

Started by John in LPC20006 years ago 9 replies

Hello! Sorry for my bad English! I need help. =) I write files on the SD card. I am using a filesystem from Keil. When I set the Base...

Hello! Sorry for my bad English! I need help. =) I write files on the SD card. I am using a filesystem from Keil. When I set the Base address of Cache Buffer in USB RAM - everything OK. But when I set the Base address in SDRAM (EMC) - its not work! I have a question - is the DMA of LPC2478 can to transmit data from the MCI FIFO to SDRAM? Or it can only transmit from the MCI FIFO to USB ...


LPC2148 SPI SCK

Started by medw...@... in LPC200012 years ago

Hello, Thanks for the quick response and information, I had noticed that there was a FIFO on the SSP but was wondering how big it was (the...

Hello, Thanks for the quick response and information, I had noticed that there was a FIFO on the SSP but was wondering how big it was (the manual doesn't mention). Much appreciated! Will try your suggestions over the weekend and report back. Any thoughts on the SPI0 clock? It seemed unlikely that such a fundimental feature of the chip would not work but


UART0 interrupts without FIFOs

Started by bacalaoencebollao in LPC200012 years ago 69 replies

I have a problem with my programme, i want to make my UART work, but without the FIFOs, is there anyway to get a receive interrupt when only one...

I have a problem with my programme, i want to make my UART work, but without the FIFOs, is there anyway to get a receive interrupt when only one character has been recieved, or do I have to wait for the FIFO to be full? In the case of using TIMEOUT, how do I fix that TIMEOUT value? Thanks


THS1206

Started by this_ip_address in LPC20009 years ago 4 replies

Hi all, Does anybody have an experience working with THS1206 (12-bit ADC from TI) or similar, like THS1006? This is a 4-chan device with...

Hi all, Does anybody have an experience working with THS1206 (12-bit ADC from TI) or similar, like THS1006? This is a 4-chan device with parallel interface and FIFO. We already wasted the whole week trying to interface it with LPC2387 (timing problems). Thank you for any input. ------------------------------------