Questions on the UART Interface

Started by Leighton Rowe in LPC200013 years ago 12 replies

Just for clarification on the UART Block Diagram (see UM)... 1. Do U0TSR & U0RSR actually representthe Tx & Rx FIFO buffers? I ...

Just for clarification on the UART Block Diagram (see UM)... 1. Do U0TSR & U0RSR actually representthe Tx & Rx FIFO buffers? I only see U0TSR & U0RSR illustrated here and I can't find any other documentation for it. Now concerning U0THR & U0RBR (data r


LPC 2368 UART

Started by suvidhk in LPC200011 years ago

I observed foll. behavior for the UART0 of LPC2368 : 1) Even if the FIFO is on I get an interrupt for receive data available for a single char...

I observed foll. behavior for the UART0 of LPC2368 : 1) Even if the FIFO is on I get an interrupt for receive data available for a single char instead of receive character time out. 2) When the transmitter empty interrupt comes and I have nothing to send and I do not disable the THRE interrupt yet it never occurs again unless I load some data and transmitter is empty again. The first b...


LPC2468 & SC16IS752 DUART Anomaly

Started by KM Shore in LPC20009 years ago 2 replies

I am using both of these NXP parts with the DUART connected via one of the i2c busses to the 2468. After long periods of moderate traffic ...

I am using both of these NXP parts with the DUART connected via one of the i2c busses to the 2468. After long periods of moderate traffic (short bursts of 20 or fewer characters, followed by a few seconds of no traffic), the DUART will set an interrupt; the status(IIR) indicates that a stale character is in the receive FIFO. When the DUART is queried both the LSR and input character count (...


jpeg encoder

Started by Sergio Sider in LPC20008 years ago 8 replies

Hi All, I have a project to make a camera log images (CIF resolution is ok) to a SD-Card, about 4 fps is ok. As it have to keep at least a...

Hi All, I have a project to make a camera log images (CIF resolution is ok) to a SD-Card, about 4 fps is ok. As it have to keep at least a full day of images, on-the-fly compression is required. I was planning to use a FIFO buffer (like AL440) to interface the camera and software jpeg compression. My question is: Did anyone work with jpeg compression using ARM7? I am afraid I could no...


EFSL and SDHC

Started by drproton2003 in LPC20009 years ago 12 replies

Hello everyone, I am attempting to get EFSL to work with SDHC cards. I have downloaded version 0.2.9 RC7 from this page...

Hello everyone, I am attempting to get EFSL to work with SDHC cards. I have downloaded version 0.2.9 RC7 from this page http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/arm_memcards/ After realizing that I needed to use the SSP FIFO mode I had it working with a 1GB SD card. Now that I am using a SDHC card I am having some problems. The problems start in the sd_Init funct...


Re: RS485 with UART1 RTS pin on LPC2138

Started by sengoontoh in LPC200013 years ago

How would you implement an interrupt based 485 handler then? I guess I could look for the byte that I transmitted. Hopefully the FIFO won't ...

How would you implement an interrupt based 485 handler then? I guess I could look for the byte that I transmitted. Hopefully the FIFO won't complicate issues. --- In lpc2000@lpc2..., "Karl Olsen" wrote: > --- In lpc2000@lpc2..., "gvnn77" wrote: > > > I'm searching for implem


SSP LPC2148

Started by mgiaco82 in LPC200010 years ago 5 replies

Hello I have some questions concerning the SSP on the LPC2148. I need to speak with one ADC and one DAC. So therefore I need 2 slave...

Hello I have some questions concerning the SSP on the LPC2148. I need to speak with one ADC and one DAC. So therefore I need 2 slave select pins. But the LPC has only one. I know that I can use a normal GPIO for slave select, but I want to use the FIFO for TX and RX. Let me explain. When I speak to the ADC (8Ch x 16Bit) I need to write 8 word commands one for each CH. After each command th...


lpc2148 isp double command answer

Started by "jul...@ymail.com" in LPC20007 years ago 2 replies

Hi, I am seeing an odd issue while trying to program a lpc2148 in ISP-mode from a lpc2103. Actually I use the UART0 of the lpc2103 with FIFO...

Hi, I am seeing an odd issue while trying to program a lpc2148 in ISP-mode from a lpc2103. Actually I use the UART0 of the lpc2103 with FIFO enabled but without interrupts (doing synchronous reading/writing). If I send the sync byte '?' to the lpc2148 I get the "Synchronized\r\n" as expected. Then I answer with "Synchronized\r\n". According to the specs I would await to get a "OK\r\n" immediat...


lpc2387 uart2 problem

Started by "sum...@yahoo.com [lpc2000]" in LPC20002 years ago 1 reply

below is my UART2 code is not working please suggest me what I am missing PCONP |= 1 <

below is my UART2 code is not working please suggest me what I am missing PCONP |= 1 <


UART0 and UART1

Started by Mukund Deshmukh in LPC200012 years ago 1 reply

Hi, Any idea on how to read FIFO buffer, on UART0 and UART1, without using interrupt? Best Regards, Mukund Deshmukh. Beta Computronics Pvt...

Hi, Any idea on how to read FIFO buffer, on UART0 and UART1, without using interrupt? Best Regards, Mukund Deshmukh. Beta Computronics Pvt Ltd 10/1, IT Park, Parsodi, Nagpur-440022 Cell - 9422113746 ------------------------ Yahoo! Groups Sponsor --------------------~--> Great things are happening at Yahoo! Groups. See the new email design. http://us.click.yahoo.com/TISQkA/hOaOAA/


Philips SPI1 confusion

Started by gen_4p in LPC200011 years ago 4 replies

Hello, I am working on some SPI routines on SSP port (lpc2148) and need some sanity check. Approach for sending data is quite standard and...

Hello, I am working on some SPI routines on SSP port (lpc2148) and need some sanity check. Approach for sending data is quite standard and straightforward - - check if transmit FIFO is not full - write a byte to data register - wait for the end of transmittion (busy flag cleared) Nevertheless that is what I see in Philips provided code. 1. From ../files/LPC214x_LPC213x Sample Code for...


LPC23xx UARTx CTI interrupt problem

Started by Ilian in LPC200011 years ago 2 replies

Hi, I'm using UART2 on my LPC2368 board to receive data from other device. I note that sometimes uart is blocking. The CTI interrupt is...

Hi, I'm using UART2 on my LPC2368 board to receive data from other device. I note that sometimes uart is blocking. The CTI interrupt is always assetred LSR register indicate there is no data in FIFO (i.e. RDR bit = 0) and the interrutp can not be cleared (read from UxRBR). And this crash my system. I investigate problem and I've found this is general BUG in LPC and in ARM. There is a prob...


recieving and parsing configuration values via uart0

Started by nerdinrage in LPC20009 years ago 1 reply

I'm working on a project requiring eight I2C registers to be set for data acquisition purposes. I have a question about the process of delivering...

I'm working on a project requiring eight I2C registers to be set for data acquisition purposes. I have a question about the process of delivering my configuration settings to the LPC2148 via the com port. I want to send a string of values delimited with commas, nothing huge something like; 0x0f,0x2c,0x45,0x12,0x67,0x99,0xab,0x33!. Since the buffer is in FIFO it will read the 0x0f first. The ! ...


FTDI chip interface problem with LPC2194 microcontroller

Started by vishal_arora82 in LPC200011 years ago 6 replies

Dear Fellow Members, I am not quite sure that is it the good to post this question here in this forum. But I have no other choice. I am...

Dear Fellow Members, I am not quite sure that is it the good to post this question here in this forum. But I have no other choice. I am working on a project implementing FIFO interface between ftdi USB chip (ft245bm) and LPC2194. I am using I/O Port 1 of LPC2194 for databus and I/O Port0 for control bus. I hope anyone of you might have worked on ftdi chips Now I am really stuck on a v...


Serial Port Interrupt

Started by jamesasteres in LPC200013 years ago 5 replies

In using the serial port (UART0) I found that simply enabling the THRE interrupt does not cause an interrupt to be asserted. ...

In using the serial port (UART0) I found that simply enabling the THRE interrupt does not cause an interrupt to be asserted. Apparently only when the TX FIFO transistions to empty does the interrupt get asserted. I know the VIC and UART0 hardware are set- up correctly since


SSP interrupts as SPIF behavior

Started by Tom Walsh in LPC200011 years ago 9 replies

Hello, I've some confusion as to how the interrupts on the SSP operate and don't seem to find any documentation regarding this. From the...

Hello, I've some confusion as to how the interrupts on the SSP operate and don't seem to find any documentation regarding this. From the documentation I've found so far, the SSP interrupt system (as documented) appears to be useless in determining when the TX FIFO is empty? I have an interrupt driven SPI state machine which I now need to move over to the SSP circuit. This state mac...


FreeRTOS and high speed UARTs of LPC210x

Started by stevec in LPC20007 years ago 1 reply

Testing FreeRTOS on LPC2106 with both UART channels outputting at 115K baud. I'm using the transmit FIFOs, so the interrupt rate is 1/16th what...

Testing FreeRTOS on LPC2106 with both UART channels outputting at 115K baud. I'm using the transmit FIFOs, so the interrupt rate is 1/16th what it would be without FIFOs (I'm amazed at how rarely I see sample code using the FIFO or using it such that it cannot do its purpose). The issue and question is: I'm using the FreeRTOS message queue to service the transmit UARTs. With message queues o...


RS-485 direction switching with LPC2138/2148

Started by tilmannreh in LPC20007 years ago 10 replies

Hello, I have designed a board with the LPC2148 that has RS-232 and RS-485 interfaces as jumper-selectable alternatives. When it comes to...

Hello, I have designed a board with the LPC2148 that has RS-232 and RS-485 interfaces as jumper-selectable alternatives. When it comes to switching the RS-485 transmitter enable, a problem arises. Even if I don't make use of the transmit FIFO and so the THRE status is somewhat delayed, the interrupt by THRE occurs too early for correct direction switching: the stop bit is cut off, so it's no...


SSP module - interrupt flag clear problem

Started by samiehg in LPC200010 years ago

Hi I am using the SSP module for TI Synch Serial frame format. Each frame size is 16-bits. For rx interrupts, the user manual suggests that...

Hi I am using the SSP module for TI Synch Serial frame format. Each frame size is 16-bits. For rx interrupts, the user manual suggests that RXIM in SSP1MSC register is to trigger an interrupt when the Rx fifo is at least half full. It is my understanding that in this way, I will get an interrupt when I have received FOUR 16-bit words. However, I have noticed the interrupt flag RXMIS ge...


UART TX FIFO, INTs problem

Started by microbit in LPC200014 years ago 4 replies

Hi all,   I'm a bit stuck with this one, and hope someone has some advice, I must be overlooking something and I...

Hi all,   I'm a bit stuck with this one, and hope someone has some advice, I must be overlooking something and I just don't see it.......   I'm using Two 256 byte circu