SSP - LPC2148

Started by mgiaco82 in LPC200011 years ago 1 reply

Hello I need some help how to program it in a good style! Device LPC2148 which must communicate with an ADC and a DAC on SPI1. I need to...

Hello I need some help how to program it in a good style! Device LPC2148 which must communicate with an ADC and a DAC on SPI1. I need to sample an 8 channel 16Bit ADC with 10 kHz at the same sample frequency I must speak to a 4 channel 16Bit DAC.(some digital control loops). Also the processor should do a lot of other stuff too. So I want to use the FIFO on SPI1 for that or ?is there som...


RS485 9 Bit Comms on LPC2148

Started by mhoneywill in LPC200012 years ago 4 replies

Hi, I'm implementing a comms protocol which requires RS485 half duplex comms with a 9 bit data word for the first byte. I'm new to the...

Hi, I'm implementing a comms protocol which requires RS485 half duplex comms with a 9 bit data word for the first byte. I'm new to the LPC214x chips so was wondering if anyone could give me some pointers. My thoughts are described below. Half Duplex Comms It looks like UART0 and UART1 have both FIFO empty and ShiftRegister empty Flags, IF you enable the THRE in


Re: LPC2000 UART drops characters silently?

Started by jayasooriah in LPC200012 years ago 48 replies

System is LPC2292; XTAL = 14.7456 MHz; PLL disabled; MAM disabled; VPBDIV = 1; UART = 8-data, 1-stop, no-parity, FIFO enabled. Symptom are...

System is LPC2292; XTAL = 14.7456 MHz; PLL disabled; MAM disabled; VPBDIV = 1; UART = 8-data, 1-stop, no-parity, FIFO enabled. Symptom are that for certain (low) baud rates, UART silently drops characters on Rx channel when saturated. There is no indication of this in the LSR and none of the error bits (OE|PE|FE|BI|RXFE) are set when this happens. It appears that UART logic is failing t...


EP_RAMsize and Words and bytes

Started by Manisha in LPC200012 years ago 2 replies

Hi all, i am confused with the words and byte relation in EP_RAM size. they are saying EP_RAM is word aligned. and FIFO maximum size is in...

Hi all, i am confused with the words and byte relation in EP_RAM size. they are saying EP_RAM is word aligned. and FIFO maximum size is in bytes, so, we will have to align the allocation. however, they ary making it as EP_RAMsize=(Maxpacketsize + 3) / 4 + 1, in this are they taking 1 word=4 bytes? but as i know 1 word, in most cases we define as 2 bytes and DWORD 4 bytes. Thanks for going


SSP as SPI Slave (LPC2148) strange behaviour

Started by xyphro4 in LPC200011 years ago 3 replies

Hello! I'm currently trying to use the SSP of an LPC2148 as SPI Slave. I set it up with theese values: [code] PINSEL1 = 0x000002A8; ...

Hello! I'm currently trying to use the SSP of an LPC2148 as SPI Slave. I set it up with theese values: [code] PINSEL1 = 0x000002A8; SSPCR0 = 0x0007; // selects CPHA=0, CPOL=0 and 8 Bit width SSPCR1 = 0x0006; // SSP enabled as Slave [/code] I receive data using polling with this small function: [code] while (1) { if (SSPSR & (1<<2)) // If SSP-RX FIFO is NOT e


How careful should you be with reserved bits?

Started by ttl_idiot in LPC20007 years ago 91 replies

Example: UART1 FIFO Control Register (U1FCR - 0xE001 0008) U1FCR |= 0x02; // Hazardous or not? This register's bits 3, 4 and 5 have the...

Example: UART1 FIFO Control Register (U1FCR - 0xE001 0008) U1FCR |= 0x02; // Hazardous or not? This register's bits 3, 4 and 5 have the following description: "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined." So, the code above could potentially read 1:s for bits 3, 4 and 5, and then write those 1:s back after OR-ing ...


peripheral INT on LPC2148 EN/DIS on the fly

Started by Jan Szymanski in LPC200012 years ago

I use SSP on LPC2148 to drive the audio codec. It works fine with TX FIFO at least half empty interrupt. Means initializes OK and runs well if...

I use SSP on LPC2148 to drive the audio codec. It works fine with TX FIFO at least half empty interrupt. Means initializes OK and runs well if untouched. However, when I tried to disable and later enable that interrupt from the software, I doesn't work reliably. I use VICIntEnable = 0x800; // enable SSP interrupt and VICIntEnClr = 0x800; // disable SSP interrupt I have tried diffe...


about i2s of LPC2378

Started by sukhdeep singh in LPC20009 years ago

hi, =A0=A0=A0=A0=A0 i am interfacing LPC2378 with 24 bit adc. adc is operating = in slave mode. now i want operate lpc2378 in master mode. what...

hi, =A0=A0=A0=A0=A0 i am interfacing LPC2378 with 24 bit adc. adc is operating = in slave mode. now i want operate lpc2378 in master mode. what should i=A0u= se in programming=A0I2SDAI or I2SDAO of i2s,second thing is that i want to = pick data of left and right channel of adc. how can i set the number of FIF= O registers. where will be the data of left and right channel in FIFO. what= shou...


Re: LPC2000 UART drops characters silently?

Started by Leon Heller in LPC200012 years ago

----- Original Message ----- From: "Peter Jakacki" To: Sent: Saturday, July 15, 2006 12:14 PM Subject: Re: [lpc2000] re: LPC2000 UART...

----- Original Message ----- From: "Peter Jakacki" To: Sent: Saturday, July 15, 2006 12:14 PM Subject: Re: [lpc2000] re: LPC2000 UART drops characters silently? > jayasooriah wrote: > > System is LPC2292; XTAL = 14.7456 MHz; PLL disabled; MAM disabled; > > VPBDIV = 1; UART = 8-data, 1-stop, no-parity, FIFO enabled. > > > > Symptom are that for certain


The uart of LPC2366 don't transmit data continuely

Started by Hieagle in LPC20008 years ago 7 replies

Hi, Can someone help me please. I use KEIL uvision and ulink2 to test the uart of lpc2366. There are a data packet of fifteen bytes to...

Hi, Can someone help me please. I use KEIL uvision and ulink2 to test the uart of lpc2366. There are a data packet of fifteen bytes to tranmit by uart of LPC2366 each second. When I use the program below: for(i=0;i


LPC2468 MCI rx fifo overruns when using both GPDMA channels

Started by lpc2xxx in LPC200010 years ago 3 replies

Hi I'm using an Embedded Artists LPC2468 board for development. Part of my application requires a large amount of data (e.g. 1GB) to be read...

Hi I'm using an Embedded Artists LPC2468 board for development. Part of my application requires a large amount of data (e.g. 1GB) to be read from SD card, processed and written to an external hi-speed USB interface. I buffer data in external SDRAM. CCLK is 48MHz. MCLK is 24MHz. I use 4-bit mode for the SD Card (i.e. 96MHz bandwidth). MCI uses GPDMA channel 0 (high priority). External...


Reading multiple bytes looks impossible from an LPC2114 SPI slave

Started by lpcarmed in LPC200011 years ago

I looked at how an SPI slave can be implemented on LPC2114. After reading the specs it appears the TX register does not have a buffer or FIFO....

I looked at how an SPI slave can be implemented on LPC2114. After reading the specs it appears the TX register does not have a buffer or FIFO. If a multiple byte transfer is needed from slave to host it's almost impossible to load data fast enough when the TX register is just emptied and the interrupt is fired. The issue is the master clock relentlessly running and the ISR is not fast enough ...


SSP: what is the interest of the Receive TimeOut flag? (RTIM in SSPIMSC registe)

Started by croquettegnu in LPC200011 years ago

Hi all, I do not understand the behavior and utility of the RTIM bit in the SSPIMSC register. It describes that a receive timeout occurs. I...

Hi all, I do not understand the behavior and utility of the RTIM bit in the SSPIMSC register. It describes that a receive timeout occurs. I don't understand the conditions that provoke this rising... Here is the extract from the datasheet: Software should set this bit to enable interrupt when a Receive Timeout condition occurs. A Receive Timeout occurs when the Rx FIFO is not empty, and...