SSP module - interrupt flag clear problem

Started by samiehg in LPC200012 years ago

Hi I am using the SSP module for TI Synch Serial frame format. Each frame size is 16-bits. For rx interrupts, the user manual suggests that...

Hi I am using the SSP module for TI Synch Serial frame format. Each frame size is 16-bits. For rx interrupts, the user manual suggests that RXIM in SSP1MSC register is to trigger an interrupt when the Rx fifo is at least half full. It is my understanding that in this way, I will get an interrupt when I have received FOUR 16-bit words. However, I have noticed the interrupt flag RXMIS ge...


SPI, SSP on LPC2148 MCB2140 Keil Bug?

Started by highgatematem28 in LPC200014 years ago 1 reply

Hi All, Has anyone set up the SPI or SSP on the LPC2148? I cant get SPI0 to work at all, i.e. no SCK when I scope the dev board (I...

Hi All, Has anyone set up the SPI or SSP on the LPC2148? I cant get SPI0 to work at all, i.e. no SCK when I scope the dev board (I have pull ups on SCK, MOSI0, MOI0 & SSEL0) and it is turned on in the power reg. void SPI_Init (void) { PINSEL0 = 0x00005500; // SPI Pins IODIR0 = 0x00000400; // Chipselect S0SPCCR =


LPC2148 SSP FIFO manipulation

Started by deliconn in LPC200014 years ago

I am using the SSP on the LPC2148 as a buffered SPI interface to a custom CPLD design. I love the FIFO for transactions where I only need to...

I am using the SSP on the LPC2148 as a buffered SPI interface to a custom CPLD design. I love the FIFO for transactions where I only need to write to the CPLD. But when I need to read from it, I find that I need to do a full buffer flush with 8 read of SSPDR for before I execute my read. This seems like such a waste. Is there an easier way to flush the FIFO? Is there a way to have acc


DMA & SSP big endian

Started by almagor100 in LPC200010 years ago 2 replies

Hi, I'm using LPC2478. My board connected to Analog Device ADE7878 chip that has Fast SPI that send continusly data. Its 3 wire protocol that...

Hi, I'm using LPC2478. My board connected to Analog Device ADE7878 chip that has Fast SPI that send continusly data. Its 3 wire protocol that start the CS bit then clock out 7*32 bits (total 7*4 bytes=28 bytes) then raise the CS - wait 30Micro Second and start again. The Clock is about 4mhz. I want to fill a large area (in sdram) with the data. I use the DMA with SSP and it works perfect. I...


SSP in SPI slave mode

Started by Gus in LPC200014 years ago 1 reply

I having many difficulties with SSP running in slave SPI mode. Has anyone luck with using it in slave SPI mode? Why you need to set the clock...

I having many difficulties with SSP running in slave SPI mode. Has anyone luck with using it in slave SPI mode? Why you need to set the clock divider (SSPCPSR)in slave mode!!??!! When I set it to different values I get different outcome but it never work right. I can use it in pooled mode no problem but I am writing an interrupt driver with 256 bytes for RX and TX. Any pointers would be


SSP Clock Rate

Started by javida13 in LPC200014 years ago 1 reply

I'm using the SSP port as an SPI and verifing operation by using the Keil uVision3. Pclk is set to 15Mhz and with this I'm seeing a clock ...

I'm using the SSP port as an SPI and verifing operation by using the Keil uVision3. Pclk is set to 15Mhz and with this I'm seeing a clock of 58,593 out of reset. After executing SSPCR0 = 0x0E87 (where SCR = 15), the clock rate changes to 3906. What I'm seeing is 58593/(SCR) The bit frequency is defined as PCLK / (CPSDVSR * (SCR+1)). CPSDVSR is set to 0 (de


Improve LPC2000 SSP port

Started by jones3hsu in LPC200014 years ago

Dear Philips Experts : I have a suggestion which to add frame signal to SSP port (SPI interface). We can use SPI interface for...

Dear Philips Experts : I have a suggestion which to add frame signal to SSP port (SPI interface). We can use SPI interface for EEPROM,SD/MMC card..... but we still need one GPIO to do CS (chip select),and frame signal can generate CS automatic. Another application is for I2S interface.and we can connect I2S device chip directly.


LPC2103 SSP port as SPI1 SCK1 problem

Started by markozivic in LPC200012 years ago 3 replies

Hi All, I have a problem with SCK1 signal on SSP (SPI1) port on LPC2103. When I look at this signal with oscilloscope it is always LOW, as...

Hi All, I have a problem with SCK1 signal on SSP (SPI1) port on LPC2103. When I look at this signal with oscilloscope it is always LOW, as if there is no communication. But at the same time SSEL1 and MOSI1 pins have waveforms as I expected. I have verified that on MOSI1 I have exactly what I'm trying to send and that signal timing is right. I have also set GPIO pin direction for SCK1 as o...


MBC2140 SD/MMC example code?

Started by Frits in LPC200014 years ago 2 replies

Hi Guys, The MBC2140 has an SD/MMC slot which is handled by the SSP controller. Does any one have some example code for using the SSP...

Hi Guys, The MBC2140 has an SD/MMC slot which is handled by the SSP controller. Does any one have some example code for using the SSP controller in SPI mode for LPC2148? There are examples for using the MBC2140 as a HID device or as a mass storage device which work great. But it would be nice to use any SD/MMC card as a mass storage


SPI / SSP driving SSEL signal as Master in LPC2148 applications

Started by Owen Edwards in LPC200010 years ago 8 replies

I'm using the SparkFun Logomatic V2 board to read LIS302 accelerometers over SPI (using the SSP port), basing my code on the KinetaMap code (also...

I'm using the SparkFun Logomatic V2 board to read LIS302 accelerometers over SPI (using the SSP port), basing my code on the KinetaMap code (also from SparkFun). Now that I have it working (and have a reasonable understanding of SPI bus operation), I'm curious why in so many LPC214x applications using SPI in Master mode (including the Logomatic's and KinetaMap's access of the SD/MMC card), the SS...


LPC214x: Can we really manage the SSP (SPI mode) in interrupt mode????

Started by croquettegnu in LPC200012 years ago 2 replies

Hi All, I'm really confused on how to deal with the SSP interrupts to manage my SPI transfers. There are two flags called RXIM and TXIM that...

Hi All, I'm really confused on how to deal with the SSP interrupts to manage my SPI transfers. There are two flags called RXIM and TXIM that allows to trig an interrupt as soon as the TX FIFO is half empty and the Rx FIFO is half full. These are the only flags that can be used to generate an interrupt (except error flags). But I do NOT understand how to manage my transfer with such inter...


Simultaneous use of SSP and SPI ports on LPC1700

Started by ksdoubleshooter in LPC20007 years ago 12 replies

I have a project using an LPC1768. This project has a requirement for 7 UART's, so I used three UART's on the LPC1768 and added two SC16IS752's,...

I have a project using an LPC1768. This project has a requirement for 7 UART's, so I used three UART's on the LPC1768 and added two SC16IS752's, which are dual UART's with selectable I2C or SPI interface. I allocated SSP0 to one of the DUART's and SSP1 to the other. Each DUART has an IRQ line and I ran these back to separate EINT pins. Running the DUART's on separate SSP ports with separate interr...


ssp on LPC2148

Started by naderus2000 in LPC200013 years ago 1 reply

hi, i need a SPI bus with 15MHZ clock can work for MMC. i see that the SPI0 for lpc2148 is max to 7.5 MHZ(1/8 PLCK) & i see that SSP(SPI1) can...

hi, i need a SPI bus with 15MHZ clock can work for MMC. i see that the SPI0 for lpc2148 is max to 7.5 MHZ(1/8 PLCK) & i see that SSP(SPI1) can clock max PLCK/2 so about 30 mhz. so i want to know can i use SPI1 for MMC. becuse i read it is the motorola sPI. is it any different from normall SPI? thanks.


SSP and SPI max SCK

Started by Gus in LPC200014 years ago 1 reply

Can someone clarify my understanding please? SPI has a max SCK of 60mhz/8 in master and in salve modes? Correct? SSP has a max SCK of...

Can someone clarify my understanding please? SPI has a max SCK of 60mhz/8 in master and in salve modes? Correct? SSP has a max SCK of 60mhz/2 in master and in slave modes? And on new chips it is going to be 70mhz/2? Correct? Thanks, Gus


Filling SSP fifo after GPDMA transfer

Started by Kuba Dorzak in LPC20007 years ago 1 reply

Hi Everybody, what I am trying to do is: 1) fill fifo at slave side using CPU 2) init GPDMA for SSP slave transfer 3) wait for master to...

Hi Everybody, what I am trying to do is: 1) fill fifo at slave side using CPU 2) init GPDMA for SSP slave transfer 3) wait for master to start transfer 5) when transfers from master and slave are finished I block at slave side GPDMA channels and reload fifo (using CPU) and wait for master to send next package. This way I expect to have valid data at master side- because I fill the fif...


ARMwizard updated to version 2.1 (SPI/SSP added)

Started by Alexan_e in LPC20007 years ago

ARMwizard updated to version 2.1 , added SPI/SSP settings What is new: . Fixed: There were cases where the CCR1.0 checkboxes were not shown...

ARMwizard updated to version 2.1 , added SPI/SSP settings What is new: . Fixed: There were cases where the CCR1.0 checkboxes were not shown for PWM . Fixed: The PCLK divider range was 1/1 - 1/8 instead of 1/1 - 1/31 for LPC177x/8x . Fixed: The PWM power control bits (PCONP) were not set to turn on the peripheral in LPC177x/8x . Fixed: The ADC1 power control bits (PCONP) were not set t...


LPC2148 SPI SCK

Started by medw...@... in LPC200014 years ago

Hello, Thanks for the quick response and information, I had noticed that there was a FIFO on the SSP but was wondering how big it was (the...

Hello, Thanks for the quick response and information, I had noticed that there was a FIFO on the SSP but was wondering how big it was (the manual doesn't mention). Much appreciated! Will try your suggestions over the weekend and report back. Any thoughts on the SPI0 clock? It seemed unlikely that such a fundimental feature of the chip would not work but


Re: SSP interrupts as SPIF behavior

Started by hsch...@yahoo.com in LPC20008 years ago
SSP

Tom, Have you figured a work around on this? Can you share with your example? I faced the same problem as you did and that's what brought me to...

Tom, Have you figured a work around on this? Can you share with your example? I faced the same problem as you did and that's what brought me to this forum. I would expect that there is an interrupt for transmit buffer empty just like other modes of communication so that I can disable one slave's CS and enable another slave's CS via interrupt. ------------------------------------


LPC2148 SPI and SSP behaviour

Started by Jan Thogersen in LPC200013 years ago 3 replies

Hi, It's now my second week in the presence of a Phillips ARM processor and I must say that it really rock's! However, due to my lack of...

Hi, It's now my second week in the presence of a Phillips ARM processor and I must say that it really rock's! However, due to my lack of experience with this wonder I face some problems getting the thing to obey all my orders :-) I really appreciate the effort people are making in this mailing list to help each other and when I gain some experience I will do my best to repay my deb...


Cannot see SCK1

Started by Rangarajan Varadan in LPC20009 years ago

Hi All, Here is my SSP init routine on the LPC3250. I see a?weird clock on my SCK0 and data is steady(correct)??on MOSI0, but nothing on...

Hi All, Here is my SSP init routine on the LPC3250. I see a?weird clock on my SCK0 and data is steady(correct)??on MOSI0, but nothing on SCK1 and MOSI1. Have I missed something? Currently I do not have Slave devices, so I have let both SSELs alone (as GPIO not asserted) void init_ssp(void) { ? ? P_MUX_SET |= (1 <