Hi, I am using the MSP430F2013 chip amd was wondering wut the biggest difference was for using the ACLK and the MCLK for the...

Hi, I am using the MSP430F2013 chip amd was wondering wut the biggest difference was for using the ACLK and the MCLK for the sampling frequency of the SD16. At the moment, I am using the ACLK, but all the sample codes that I have seen use the MCLK. What is the speed of the MCLK? Is it set with the DCO? Does using ACLK slow my actual chip? Is that why when I'm debugging, my code seems ...

Dear all, I have a problem to setup the MCLK and SMCLK with FLL+ for MSP430F413, would you give me a help? The following is the code that I...

Dear all, I have a problem to setup the MCLK and SMCLK with FLL+ for MSP430F413, would you give me a help? The following is the code that I used to test the MCLK/SMCLK setting. I just try to setup the clock and then output it to P1.5 and P1.1 to check the frequency. And actually, I need a ~2 MHz MCLK void main( void ) { WDTCTL = WDTPW + WDTHOLD; // stop watchdog timer SCFI0 |= FN_4

Hi everybody I'm facing a little problem with a MSP430F449: I want to use the XT2 clock with 8MHz crystal as MCLK. I am checking the MCLK via...

Hi everybody I'm facing a little problem with a MSP430F449: I want to use the XT2 clock with 8MHz crystal as MCLK. I am checking the MCLK via P1.1 and it does not change, when the following procedure is executed : FLL_CTL1&=~0x20; // turn on XT2 oscillator while (FLL_CTL0&0x08); // wait for XT2 to stabilise FLL_CTL1|=0x10; // select XT2 as MCLK P1SEL=0x22; // output MCLK an

Hi everyone, Would like to know has anyone tried operating MCLK with only 32kHz xtal attached? From TI TimerA sample codes, it wrote there...

Hi everyone, Would like to know has anyone tried operating MCLK with only 32kHz xtal attached? From TI TimerA sample codes, it wrote there MCLK default uses DCO ~800kHz. However, when I try to trigger the Watchdog timer (WDT_MRST_32), I don't see it returning to the breakpoint I've set at the every beginning? Did I miss out anything? Please help. Thanks! :) Another qn, I'm trying to fin...

I am unable to see any output from MCLK (pin 48 on an Msp- fet430p140). I tried to set P5 to be an output ... P5 = 0x0F, but still see no...

I am unable to see any output from MCLK (pin 48 on an Msp- fet430p140). I tried to set P5 to be an output ... P5 = 0x0F, but still see no MCLK. Any ideas?

The example code you used generates a continuous train of pulses. Correct? As written, the pulse width is always half of a period and...

The example code you used generates a continuous train of pulses. Correct? As written, the pulse width is always half of a period and is determined by SMCLK and the constant +50,000. You cannot reduce the constant much below +100 because it takes a lot of MCLK periods to execute the ISR. Thus with MCLK=SMCLK=1MHz, your pulse width is about 100usec. If you increase MCLK=SMCLK to 16MHz, the p...

Hello forum members, I am using MSP430F2418 with CrossStudio. I am outputting all the three clocks - MCLK, SMCLK and ACLK. When I use DCO, I...

Hello forum members, I am using MSP430F2418 with CrossStudio. I am outputting all the three clocks - MCLK, SMCLK and ACLK. When I use DCO, I am able to output MCLK and SMCLK as ACLK is not available for DCO. But when I use external XTAL (LFXT1), I am able to output only MCLK and ACLK. There is no output on SMCLK pin. Has anyone experienced this issue with SMCLK? Here I am giving the c...

Hi, Is possible to pull the MCLK generated using DCO to an external pin for viewing? The external pin may be a large load, and so may...

Hi, Is possible to pull the MCLK generated using DCO to an external pin for viewing? The external pin may be a large load, and so may increase the rise/fall times of the MCLK, but I just want to see that the MCLK has a nice 50% duty cycle and is very clean and stable. I read over the entire section regarding Basic Clock Module Operation, but it did not mention anywhere that I can view the

Hi guys, I am using the MPS430F5438A and I want to read a external byte stream (at P6 port) to RAM. The byte stream is clocked externally. I...

Hi guys, I am using the MPS430F5438A and I want to read a external byte stream (at P6 port) to RAM. The byte stream is clocked externally. I put this CLK to P2.7 pin (DMAE0 this is DMATrigger31 signal). According to the datasheet this needs 4 MCLK's. The external CLK is asynchronous to MCLK. The question is: when is the byte at input port P6 read? In which of the 4 MCLK's? I see no ti...

Hi I'm using a MSP430F133 with 32kHz crystal on LFXT1. MCLK is set to DCO which runs at ~750kHz on startup and is synchronized to ACLK at 1.04...

Hi I'm using a MSP430F133 with 32kHz crystal on LFXT1. MCLK is set to DCO which runs at ~750kHz on startup and is synchronized to ACLK at 1.04 Mhz using Set_DCO() from TI example. After power on, everything works fine in most cases. It happens though that the cpu hangs before or after the delay loop (P2.4 is ON or P2.5 is ON). MCLK can be present at P5.4 or remains rarely at 3V3 DC. It loo...

Hi, I'm currently using an F449 with one 32kHz crystal on XT1 and one 8Mhz crystal on XT2. I used a snipset of Code from TI to use both...

Hi, I'm currently using an F449 with one 32kHz crystal on XT1 and one 8Mhz crystal on XT2. I used a snipset of Code from TI to use both crystals. My problem: MCLK is only 1.034 Mhz (probably DCO?) but SMCLK is 8MHz! I did have selected the SELM switch but it does not appear to work.. Somebody has any suggestions? Thanks Martin -----------------------------------------------------------

Hi all, After a long battle i got the high frequency clock (8MHz) from LFXT1 produced at P5.6(Aclk). I am still not able to ...

Hi all, After a long battle i got the high frequency clock (8MHz) from LFXT1 produced at P5.6(Aclk). I am still not able to configure MCLK = LFXT1 and MCLK still operates from DCO. The only thing now remaining besides configuring clock registers as below is setting SCG0 bit in SR.Has anyone gone through this pain?? I want to confirm that yo...

Hi everybody, I am working with the MSP430F16x to communicate with another device through the SPI and I think I have an error in the clock...

Hi everybody, I am working with the MSP430F16x to communicate with another device through the SPI and I think I have an error in the clock concept. I have look for it in the forum but I did=92t find the answer. I thought that the MCLK clock and the UCLK from the SPI were independent and the second one could be faster than the processor clock but it is clear that I am wrong. If I set the ...

Greetings, I am new to both the msp430 and embedded programming in general, and, as befits my status, I have a newbie question to ask. I have...

Greetings, I am new to both the msp430 and embedded programming in general, and, as befits my status, I have a newbie question to ask. I have MCLK set to DCO, and now I want to post a timer interrupt every n counts. I therefore want to use TimerA in continuous mode. The problem I have is that there doesn't seem to be any way to select the MCLK or DCOCLK as the clock source: my choices seem

Hello! I am trying to to change the frequency of MCLK (to 8.0 MHz) on the MSP430FG4618. But I cant get it to exactly to 8.0 MHz. According to my...

Hello! I am trying to to change the frequency of MCLK (to 8.0 MHz) on the MSP430FG4618. But I cant get it to exactly to 8.0 MHz. According to my calculations, N should be 121, but am having to hard time figuring it out. Here is my code: #include void main (void) { WDTCTL = WDTHOLD | WDTPW; //Stop Watchdog Timer P1DIR |= BIT1; //set port pin P1.1 to output directi

Trying to use 12bit ADC12 in a MSP430F449 on a Softbaugh BLCDA2 dev board. Configuring ADC12 similar to TI's sample code ads12_02.c Using...

Trying to use 12bit ADC12 in a MSP430F449 on a Softbaugh BLCDA2 dev board. Configuring ADC12 similar to TI's sample code ads12_02.c Using internal 2.5V ref. Using P6.0 as the input MCLK is 8Mhz, derived off a 32Khz crystal ADC12 clock is MCLK/2 (4Mhz) Using Extended Sample Mode, with ADC12SC bit controlling conversions. If I feed P6.0 with a stiff variable voltage, for most values, the AD

Hi group- My MSP430F449 application requires approx 500KHz MCLK. I'm using a 32768Hz crystal at XIN and XOUT with external 18pF caps. By...

Hi group- My MSP430F449 application requires approx 500KHz MCLK. I'm using a 32768Hz crystal at XIN and XOUT with external 18pF caps. By incrementally decreasing SCFQCTL, I'm able to lower MCLK. Refer to the following code snippet I use (IAR compiler): SCFQCTL = SCFQ_1M; SCFI0 = FLLD_1; SCFI1 = 0; FLL_CTL0 = DCOPLUS; FLL_CTL1 = XT2OFF | SELM_DCO | FLL_DIV_1; If I change SCFQCTL to

Looking at the piece of code provided, I've seen no delay for clock stabilization. Have you provided it? It's important to generate such...

Looking at the piece of code provided, I've seen no delay for clock stabilization. Have you provided it? It's important to generate such delay before changing the clock source from DCO to XT2, at least it says so in the MSP430x1xx User's Guide. Probably that 6-MHz frequency on the MCLK comes from the DCO, and not the XT2. Adriano. ----- Original Message ----- From: Sipke de Leeuw

Hi All I am perusing the '449 manual (SLAU056C) and in the digital IO section it says 'An external interrupt event should be at least 1.5...

Hi All I am perusing the '449 manual (SLAU056C) and in the digital IO section it says 'An external interrupt event should be at least 1.5 times MCLK or longer, to ensure it is accepted...' Does this mean that the external interrupt can not be used to exit low power mode, since MCLK is turned off in all low power modes? Regards David Bagnara

Hi everyone, Do anyone know how I can select module port function on MSP430449 at port P1, pins P1.1, P1.3, P1.4, P1.5? I want to select...

Hi everyone, Do anyone know how I can select module port function on MSP430449 at port P1, pins P1.1, P1.3, P1.4, P1.5? I want to select TA0 on P1.1! I tried with P1SEL and P!DIR, but I always get third function of the pin (for P1.1 I get MCLK). P1.0/TA0 P1.1/TA0/MCLK - I want TA0 P1.2/TA1 P1.3/TBOutH/SVSOut - I want TBOutH P1.4/TBCLK/SMCLK - I want TBCLK P1.5/TACLK/ACLK