ACLK vs MCLK

Started by mel88y in MSP43010 years ago 5 replies

Hi, I am using the MSP430F2013 chip amd was wondering wut the biggest difference was for using the ACLK and the MCLK for the...

Hi, I am using the MSP430F2013 chip amd was wondering wut the biggest difference was for using the ACLK and the MCLK for the sampling frequency of the SD16. At the moment, I am using the ACLK, but all the sample codes that I have seen use the MCLK. What is the speed of the MCLK? Is it set with the DCO? Does using ACLK slow my actual chip? Is that why when I'm debugging, my code seems ...


How to setup MCLK/SMCLK with FLL+?

Started by To chi kin in MSP43015 years ago

Dear all, I have a problem to setup the MCLK and SMCLK with FLL+ for MSP430F413, would you give me a help? The following is the code that I...

Dear all, I have a problem to setup the MCLK and SMCLK with FLL+ for MSP430F413, would you give me a help? The following is the code that I used to test the MCLK/SMCLK setting. I just try to setup the clock and then output it to P1.5 and P1.1 to check the frequency. And actually, I need a ~2 MHz MCLK void main( void ) { WDTCTL = WDTPW + WDTHOLD; // stop watchdog timer SCFI0 |= FN_4


XT2 clock

Started by Christian Epp in MSP43014 years ago 2 replies

Hi everybody I'm facing a little problem with a MSP430F449: I want to use the XT2 clock with 8MHz crystal as MCLK. I am checking the MCLK via...

Hi everybody I'm facing a little problem with a MSP430F449: I want to use the XT2 clock with 8MHz crystal as MCLK. I am checking the MCLK via P1.1 and it does not change, when the following procedure is executed : FLL_CTL1&=~0x20; // turn on XT2 oscillator while (FLL_CTL0&0x08); // wait for XT2 to stabilise FLL_CTL1|=0x10; // select XT2 as MCLK P1SEL=0x22; // output MCLK an


MSP430F149 MCLK using 32kHz?

Started by Genevieve in MSP4309 years ago 1 reply

Hi everyone, Would like to know has anyone tried operating MCLK with only 32kHz xtal attached? From TI TimerA sample codes, it wrote there...

Hi everyone, Would like to know has anyone tried operating MCLK with only 32kHz xtal attached? From TI TimerA sample codes, it wrote there MCLK default uses DCO ~800kHz. However, when I try to trigger the Watchdog timer (WDT_MRST_32), I don't see it returning to the breakpoint I've set at the every beginning? Did I miss out anything? Please help. Thanks! :) Another qn, I'm trying to fin...


XTAL - the oscillator

Started by mike2forums in MSP4308 years ago 12 replies

Hello Forum members, I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock...

Hello Forum members, I am using MSP430F2618 with a XTAL of 1MHz connected to XT1 pins. The bus clock (MCLK) is 250KHz while the aux clock (ACLK) is 1MHz. I am using ACLK to different peripherals like UART, SPI, timer etc. Is it possible that the timer execution will get affected as the MCLK and ACLK differ very much - i.e. ACLK = four times MCLK? MCLK will be used to execute the instructions...


MSP430F140 use MCLK w 32kHz Xtal

Started by Genevieve in MSP4309 years ago

Hi everyone, Would like to know has anyone tried operating MCLK with only 32kHz xtal attached? From TI TimerA sample codes, it wrote there...

Hi everyone, Would like to know has anyone tried operating MCLK with only 32kHz xtal attached? From TI TimerA sample codes, it wrote there MCLK default uses DCO ~800kHz. However, when I try to trigger the Watchdog timer (WDT_MRST_32), I don't see it returning to the breakpoint I've set at the every beginning? Did I miss out anything? Please help. Thank you in advance! Cheers, Gene


MCLK output

Started by cteise in MSP43014 years ago 36 replies

I am unable to see any output from MCLK (pin 48 on an Msp- fet430p140). I tried to set P5 to be an output ... P5 = 0x0F, but still see no...

I am unable to see any output from MCLK (pin 48 on an Msp- fet430p140). I tried to set P5 to be an output ... P5 = 0x0F, but still see no MCLK. Any ideas?


Re: questions about writing on information memory

Started by Felipe H in MSP4309 years ago

> > 2.) > Since FTG is sourced by SMCLK (in your system!) MCLK doesn't matter. > I cannot think of any advantage reducing MCLK?! Since...

> > 2.) > Since FTG is sourced by SMCLK (in your system!) MCLK doesn't matter. > I cannot think of any advantage reducing MCLK?! Since writing and erasing flash consumes some cycles and the msp will be jumping to nowhere while doing this, it could be interesting to reduce MCLK to reduce power consumption. Or not? Maybe I'm thinking on a wrong way. Heuer On Tue, Mar 25, 2008 at 9:27 AM,


Re: 10 Microsecond Pulse Generation

Started by old_cow_yellow in MSP4309 years ago

The example code you used generates a continuous train of pulses. Correct? As written, the pulse width is always half of a period and...

The example code you used generates a continuous train of pulses. Correct? As written, the pulse width is always half of a period and is determined by SMCLK and the constant +50,000. You cannot reduce the constant much below +100 because it takes a lot of MCLK periods to execute the ISR. Thus with MCLK=SMCLK=1MHz, your pulse width is about 100usec. If you increase MCLK=SMCLK to 16MHz, the p...


MSP430 Clock module

Started by ti2tt in MSP4308 years ago 11 replies

Hello forum members, I am using MSP430F2418 with CrossStudio. I am outputting all the three clocks - MCLK, SMCLK and ACLK. When I use DCO, I...

Hello forum members, I am using MSP430F2418 with CrossStudio. I am outputting all the three clocks - MCLK, SMCLK and ACLK. When I use DCO, I am able to output MCLK and SMCLK as ACLK is not available for DCO. But when I use external XTAL (LFXT1), I am able to output only MCLK and ACLK. There is no output on SMCLK pin. Has anyone experienced this issue with SMCLK? Here I am giving the c...


Master Clock Signal (DCO) Viewing and abnormalities in SPI_CLK

Started by finfets in MSP43012 years ago 2 replies

Hi, Is possible to pull the MCLK generated using DCO to an external pin for viewing? The external pin may be a large load, and so may...

Hi, Is possible to pull the MCLK generated using DCO to an external pin for viewing? The external pin may be a large load, and so may increase the rise/fall times of the MCLK, but I just want to see that the MCLK has a nice 50% duty cycle and is very clean and stable. I read over the entire section regarding Basic Clock Module Operation, but it did not mention anywhere that I can view the


F5438A DMA cycle timing for external port

Started by Matthias Weingart in MSP4306 years ago 14 replies

Hi guys, I am using the MPS430F5438A and I want to read a external byte stream (at P6 port) to RAM. The byte stream is clocked externally. I...

Hi guys, I am using the MPS430F5438A and I want to read a external byte stream (at P6 port) to RAM. The byte stream is clocked externally. I put this CLK to P2.7 pin (DMAE0 this is DMATrigger31 signal). According to the datasheet this needs 4 MCLK's. The external CLK is asynchronous to MCLK. The question is: when is the byte at input port P6 read? In which of the 4 MCLK's? I see no ti...


'FE427: MCLK slow down if SD16 analog input increase saturation

Started by Kaiman97 in MSP43012 years ago

A very strange behaviour: I have an external 32768 Hz crystal that generates a 8.3 MHz MCLK. The SD16 has an external (TCLK) clock source @...

A very strange behaviour: I have an external 32768 Hz crystal that generates a 8.3 MHz MCLK. The SD16 has an external (TCLK) clock source @ 5.6448 MHz (fM=705.6 KHz). I send a 1 KHz waveform (sinusoide) to the differential SD16 pins, everything works fine BUT if I increase the ampliture of the waveform, and saturation reaches 50/60% of the period, the MCLK slows down to 7.1 MHz !!!!! Pow


Startup problem with F133

Started by Stefan Gysel in MSP4308 years ago 6 replies

Hi I'm using a MSP430F133 with 32kHz crystal on LFXT1. MCLK is set to DCO which runs at ~750kHz on startup and is synchronized to ACLK at 1.04...

Hi I'm using a MSP430F133 with 32kHz crystal on LFXT1. MCLK is set to DCO which runs at ~750kHz on startup and is synchronized to ACLK at 1.04 Mhz using Set_DCO() from TI example. After power on, everything works fine in most cases. It happens though that the cpu hangs before or after the delay loop (P2.4 is ON or P2.5 is ON). MCLK can be present at P5.4 or remains rarely at 3V3 DC. It loo...


Some general questions

Started by john Mcdonald in MSP43013 years ago

June 5, 2004 Hi all, Would someone clarify the following questions related to MSP430F449 for me please, 1- If I use the p1.1 in as a...

June 5, 2004 Hi all, Would someone clarify the following questions related to MSP430F449 for me please, 1- If I use the p1.1 in as a mean of MCLK can I still use the same pin for the Boot Strap Loader?, 2- Could SMCLK be programmed to as high frequency as MCLK?, 3- Could you select P1.3 as SVSOUT and the P6.7 as general I/O pin since SVSin is internally connected to the AVcc? T


8Mhz MCLK on F449

Started by expresso22003 in MSP43015 years ago 2 replies

Hi, I'm currently using an F449 with one 32kHz crystal on XT1 and one 8Mhz crystal on XT2. I used a snipset of Code from TI to use both...

Hi, I'm currently using an F449 with one 32kHz crystal on XT1 and one 8Mhz crystal on XT2. I used a snipset of Code from TI to use both crystals. My problem: MCLK is only 1.034 Mhz (probably DCO?) but SMCLK is 8MHz! I did have selected the SELM switch but it does not appear to work.. Somebody has any suggestions? Thanks Martin -----------------------------------------------------------


sourcing MCLK frm external crystal

Started by Smita in MSP43012 years ago

hi all, m trying to sourch MCLK from external XT2 crystal..... m trying out the procedure provided in the user's guide datasheet. but the...

hi all, m trying to sourch MCLK from external XT2 crystal..... m trying out the procedure provided in the user's guide datasheet. but the external crystal is not getting stablised.. the OFIFG flag is not getting cleared..... wht cud be the problem..... any help wud be appreciable...... Thanks and regards.. Smita.


430F149 High frequency Config issue.....

Started by europus in MSP43010 years ago 4 replies

Hi all, After a long battle i got the high frequency clock (8MHz) from LFXT1 produced at P5.6(Aclk). I am still not able to ...

Hi all, After a long battle i got the high frequency clock (8MHz) from LFXT1 produced at P5.6(Aclk). I am still not able to configure MCLK = LFXT1 and MCLK still operates from DCO. The only thing now remaining besides configuring clock registers as below is setting SCG0 bit in SR.Has anyone gone through this pain?? I want to confirm that yo...


SPI clock faster than MCLK?

Started by in MSP4308 years ago 13 replies

Hi everybody, I am working with the MSP430F16x to communicate with another device through the SPI and I think I have an error in the clock...

Hi everybody, I am working with the MSP430F16x to communicate with another device through the SPI and I think I have an error in the clock concept. I have look for it in the forum but I did=92t find the answer. I thought that the MCLK clock and the UCLK from the SPI were independent and the second one could be faster than the processor clock but it is clear that I am wrong. If I set the ...


Newbie question: TimerA and DCOCLK

Started by pollyp100 in MSP43012 years ago 2 replies

Greetings, I am new to both the msp430 and embedded programming in general, and, as befits my status, I have a newbie question to ask. I have...

Greetings, I am new to both the msp430 and embedded programming in general, and, as befits my status, I have a newbie question to ask. I have MCLK set to DCO, and now I want to post a timer interrupt every n counts. I therefore want to use TimerA in continuous mode. The problem I have is that there doesn't seem to be any way to select the MCLK or DCOCLK as the clock source: my choices seem