I have the msp430f169 controller. I have a LFXT1=32768hz, ACLK=LFXT1CLK/8 and MCLK=SMCLK=UCLK0=DCOCLK. BCSCTL1 |= XT2OFF + DIVA_3; BCSCTL2 =...

I have the msp430f169 controller. I have a LFXT1=32768hz, ACLK=LFXT1CLK/8 and MCLK=SMCLK=UCLK0=DCOCLK. BCSCTL1 |= XT2OFF + DIVA_3; BCSCTL2 = 0; TACCTL2 = CM_1 + CCIS_1 + CAP; TACTL = TASSEL_2 + MC_2 + TACLR; CCIS_1 define the CCI2B as input signal for capture. What is CCI2B signal? Best regards, MFER

I am trying to implement a couple of C functions to erase an information segment on the MSP430F148 and then write selected words to memory,...

I am trying to implement a couple of C functions to erase an information segment on the MSP430F148 and then write selected words to memory, using the assembly example in the user manual as a guide. The system is resetting, and I am not sure where it is happening. I would appreciate any guidance you can give. The MCLK, set to 2 MHZ, is selected for the flash clock source, divided by

Hello. I am using MSP 449 in a smart plug project, no battery for microcontroller supply, 3V3 comes from mains power supply. I have the following...

Hello. I am using MSP 449 in a smart plug project, no battery for microcontroller supply, 3V3 comes from mains power supply. I have the following initialization sequence // disable_watchdog(); // Set SVS to generate POR, at Vcc < 2.8 V SVSCTL = 0u; SVSCTL = (PORON | VLD3); // Setup system clock (MCLK) @ 8 MHz do { IFG1 &= ~OFIFG; // Clear OSCFault flag

Hello all, I am using MSP130F169 and trying to calculate delay time when the 32,768 Hz crystal is switched off and when it is switched on...

Hello all, I am using MSP130F169 and trying to calculate delay time when the 32,768 Hz crystal is switched off and when it is switched on again till it acquires normal frequency (startup delay of LFXT1 whihc is sorce of ACLK). I am sourcing MCLK from DCO and then go into a timer interrupt where I wrote following code: #pragma vector=TIMERA0_VECTOR __interrupt void Timer_A0( void ...

Hi Folks, does anybody have a simple sourcecode for a sound generator (if possible in "C"). Connecting a piezo via a FET to a port of the MSP...

Hi Folks, does anybody have a simple sourcecode for a sound generator (if possible in "C"). Connecting a piezo via a FET to a port of the MSP it's no problem to produce a sounds, but I'm searching for a code to produce good, music like, sounds folling the scale to play a melody. The MSP430 is runnig with MCLK=8MHz so it should be no problem for higher frequencies. See you, Ge

So I'm having a problem with input 6 of Timer B (P4.6). I'm picking up noise on this input. It's also wired to P1.1. The odd part is that I'm...

So I'm having a problem with input 6 of Timer B (P4.6). I'm picking up noise on this input. It's also wired to P1.1. The odd part is that I'm picking up noise on P4.6, but not P1.1. The other odd part is that the frequency of the noise appears to change depending on whether I'm using an MCLK of 1MHz or 8MHz. Even odder is that when I scope the pins, I don't see any noise. So I can't even t...

I am using a 149F device, it is setup to run of an 8MHz crystal. My question is if for some reason there is an problem with the oscillator...

I am using a 149F device, it is setup to run of an 8MHz crystal. My question is if for some reason there is an problem with the oscillator and the OSC fault is detected what happens? It appears that the MCLK reverts back to run off the DCO, but then what? Will the processor run off the DCO forever unless it is set back to run off the external crystal? There is currently no ISR fo

Hi, i have two strange problems with the ADC12 in the MSP430F149: - When i set MCLK = SMCLK = ACLK = LFXT1 (=32768 Hz ) with BCSCTL2 = SELM1...

Hi, i have two strange problems with the ADC12 in the MSP430F149: - When i set MCLK = SMCLK = ACLK = LFXT1 (=32768 Hz ) with BCSCTL2 = SELM1 + SELM0; i get a hangup independent from the ADC12 core clock (tested with ACLK and ADC12OSC). With switched of ADC12 the low cpu clock is no problem. - Setting ADC12IFG = 0 at the end of the ADC12 ISR does not clear the interrupt flags; i get ap

I have one question regarding MSP430F2131 instructions execution times. According to slau144d.pdf section 3.4.4, double operand...

I have one question regarding MSP430F2131 instructions execution times. According to slau144d.pdf section 3.4.4, double operand instructions in addressing mode #N,&EDE uses 5 cycles. For example, following code would generate negative pulse on P2.5. Pulse would be 5 MCLK periods wide because those instructions consumes 5 CPU cycles. bic.b #BIT5,&P2OUT bis.b #BIT5,&P2OUT But ...

Hi All, I've problem with max SPI bus speed, I connect AT45DB041B (Atmel's pdf says: "? 20 MHz Max Clock Frequency" p.1 of...

Hi All, I've problem with max SPI bus speed, I connect AT45DB041B (Atmel's pdf says: "? 20 MHz Max Clock Frequency" p.1 of doc1918.pdf) and: couple code of SPI initialization : //--- BCSCTL1 &= ~XT2OFF; // XT2on BCSCTL2 |= SELM1+SELS; // MCLK = LFXT1 (safe) ME1 = USPIE0; // Enable SPI mode UTCTL0 = CKPH+SSEL1+SSEL0+ST

Hi all, If I'd want a 1 mSec delay and smclk/mclk = 8MHz What should mS be?? void delay_ms(int del) { //This routine is...

Hi all, If I'd want a 1 mSec delay and smclk/mclk = 8MHz What should mS be?? void delay_ms(int del) { //This routine is approx 1mS delay @ 8 MHz unsigned int ctr; while(del--) for (ctr=0; ctr < mS; ++ctr) ; } thanks, Martijn

I am working on a project that uses MSP430G2452IPW14 (14 pin TSSOP package.) At initialization, I set MCLK and SMCLK sourced from DCO and set...

I am working on a project that uses MSP430G2452IPW14 (14 pin TSSOP package.) At initialization, I set MCLK and SMCLK sourced from DCO and set DCO to my chosen clock frequency (I did not rely on Info flash segment D calibration parameters, as those didn't yield the frequency I require.) I was surprised to find upon building my second prototype of the project that the DCO frequency, using the ...

Hi all! I'm using UART0 to stablish a serial communication between my MSP430F149 and an external GPS chip. This chip needs a (8-bit...

Hi all! I'm using UART0 to stablish a serial communication between my MSP430F149 and an external GPS chip. This chip needs a (8-bit data+1stop bit) protocol at 19200 bps (my MCLK=SMCLK clock is 8MHz). I've configured the UART0 to this rate, but now I have a doubt when transmitting a data string using it. TXBUF0 transmits packets of 8bits maximum, isn't it? Then, shall I divide my st

I am using a MSP430F1121A and I cannot understand the times of instructions. I seem to have it ok but when checking on a scope I find it is...

I am using a MSP430F1121A and I cannot understand the times of instructions. I seem to have it ok but when checking on a scope I find it is not correct. I am using a 32KHz crystal and using this for MCLK. I have the following instruction bis.b #ENABLE,&P1OUT, bic.b #ENABLE,&P1OUT bis.b #ENABLE,&P1OUT. I would have thought this instruction would take 5 cycles from what I read

[code] ;******************************************************************** ; MSP-FET430P440 Demo - USART0 UART 9600 Echo ISR, DCO...

[code] ;******************************************************************** ; MSP-FET430P440 Demo - USART0 UART 9600 Echo ISR, DCO SMCLK ; ;Description;Echo a received character,RX ISR used. Normalmode->LPM0 ; USART0 RX interrupt triggers TX Echo. ; ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = UCLK0 = DCOCLK = 1048576 ; Baud rate divider with 1048576hz = 1048576Hz/9600 ~ 109 (006Dh) ; //*An

Hi, On Port 5.5 (pin 49) a want to have a rectangular 8MHz-signal. There is allready a "sine" 8MHz clock. I tested the following...

Hi, On Port 5.5 (pin 49) a want to have a rectangular 8MHz-signal. There is allready a "sine" 8MHz clock. I tested the following code: ....... SetupP bis.b #0FFh,&P4DIR ; P4 0-7 sind output bic.b #080h,&BCSCTL1 ; XT2 ON mov.b #088h,&BCSCTL2 ; MCLK=SMCLK=XT2CLK bic.b #OFIFG,&IFG1 ; Clear OFIFG bis

Here's my C code: [code] // Set main clock (MCLK) to 2.45 MHz sync'd to the 32 KHz crystal. WDTCTL = WDTPW + WDTHOLD; // Stop watchdog...

Here's my C code: [code] // Set main clock (MCLK) to 2.45 MHz sync'd to the 32 KHz crystal. WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer FLL_CTL0 |= XCAP18PF; // set load capacitance for xtal SCFI0 |= FN_2; // x2 DCO, 4MHz nominal DCO SCFQCTL = 74; // (74+1) x 32768 = 2.45Mhz // Set up Timer A to generate an interrupt every 32768 ACLK cycles (every 1 second). WDTCTL = WDTPW + WDTHO...