>
>the renowned Guy Macon <http://www.guymacon.com> wrote:
>
>>On the subject of what cost (in dollars or reliability) I am willing
>>to pay to make the test possible, the answer is "not much." The
>>chances of finding a bad gate are small and the chances of a bad
>>gate causing problems with other gates in the package that the other
>>tests cannot find are also small. The counterargument is that a
>>failure in the solder joints is also small, and is unlikely to cause
>>a system failure in most circuits.
>
>Isn't (small^2) << (small * 3) for reasonable values of small?
Yup. If I was working on a SOF (safety of flight) design right now,
I would tie all unused inputs directly to the ground plane. For a
non-SOF design I would put a short cuttable trace between the pin
and ground. I would also consider connecting unused inputs to
unused outputs. I would put in the resistor only in the case of
an unused input that requires a pullup/pulldown but could possibly
become an output, such as a typical uC port, or one that I thought
had a high probability of being called into sevice with a cut &
jumper later.
>On the subject of what cost (in dollars or reliability) I am willing
>to pay to make the test possible, the answer is "not miuch." The
>chances of finding a bad gate are small and the chances of a bad
>gate causing problems with other gates in the package that the other
>tests cannot find are also small. The counterargument is that a
>failure in the solder joints is also small, and is unlikely to cause
>a system failure in most circuits.
Isn't (small^2) << (small * 3) for reasonable values of small?
;-)
Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
>
>the renowned Guy Macon <http://www.guymacon.com> wrote:
>
>>Spehro Pefhany <speffSNIP@interlogDOTyou.knowwhat> says...
>>>
>>>Jack Klein <jackklein@spamcop.net> wrote:
>>>
>>>>On the other hand, the standards for many manufacturing organizations
>>>>these days prohibit directly connecting power pins to either logic
>>>>supply. They require a resistor in the 1K to 10K range so that they
>>>>can drive it to the opposite level in automated test fixtures.
>>>
>>>That could find faults such as the output of an unused gate shorted to
>>>the supply rail, I suppose, but there must be few reasons for testing
>>>a logic state which never occurs in normal operation.
>>
>>I disagree. I sometimes design systems where if the system fails
>>somebody (often a lot of somebodies) dies. If there is an unused
>>gate that doesn't work, I want to find it in test and replace that
>>chip; I don't trust it to not have other problems.
>
>Do you reckon that the possibility of finding that the gate input that
>you're not using has failed between component test and assembly test,
>and that will later result in a meaningful failure, is higher than the
>reliability hit caused by adding two additional solder joints and an
>additional component, the failure of any of which will likely cause an
>*intermittent* failure of the system?
I actually wrote a paragraph saying pretty much what you just wrote
but deleted it because it seemed like talking down to the audience,
assuming that the reader can't figure out failure probabilities.
I disagree with "few reasons for testing a logic state which never
occurs in normal operation." I think that there are many good
reasons for doing that.
On the subject of what cost (in dollars or reliability) I am willing
to pay to make the test possible, the answer is "not miuch." The
chances of finding a bad gate are small and the chances of a bad
gate causing problems with other gates in the package that the other
tests cannot find are also small. The counterargument is that a
failure in the solder joints is also small, and is unlikely to cause
a system failure in most circuits.
>
>Spehro Pefhany <speffSNIP@interlogDOTyou.knowwhat> says...
>>
>>Jack Klein <jackklein@spamcop.net> wrote:
>>
>>>On the other hand, the standards for many manufacturing organizations
>>>these days prohibit directly connecting power pins to either logic
>>>supply. They require a resistor in the 1K to 10K range so that they
>>>can drive it to the opposite level in automated test fixtures.
>>
>>That could find faults such as the output of an unused gate shorted to
>>the supply rail, I suppose, but there must be few reasons for testing
>>a logic state which never occurs in normal operation.
>
>I disagree. I sometimes design systems where if the system fails
>somebody (often a lot of somebodies) dies. If there is an unused
>gate that doesn't work, I want to find it in test and replace that
>chip; I don't trust it to not have other problems.
Do you reckon that the possibility of finding that the gate input that
you're not using has failed between component test and assembly test,
and that will later result in a meaningful failure, is higher than the
reliability hit caused by adding two additional solder joints and an
additional component, the failure of any of which will likely cause an
*intermittent* failure of the system?
Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
>
>Jack Klein <jackklein@spamcop.net> wrote:
>
>>On the other hand, the standards for many manufacturing organizations
>>these days prohibit directly connecting power pins to either logic
>>supply. They require a resistor in the 1K to 10K range so that they
>>can drive it to the opposite level in automated test fixtures.
>
>That could find faults such as the output of an unused gate shorted to
>the supply rail, I suppose, but there must be few reasons for testing
>a logic state which never occurs in normal operation.
I disagree. I sometimes design systems where if the system fails
somebody (often a lot of somebodies) dies. If there is an unused
gate that doesn't work, I want to find it in test and replace that
chip; I don't trust it to not have other problems.
--
Guy Macon, Electronics Engineer & Project Manager for hire.
Remember Doc Brown from the _Back to the Future_ movies? Do you
have an "impossible" engineering project that only someone like
Doc Brown can solve? My resume is at http://www.guymacon.com/
>>On the other hand, the standards for many manufacturing organizations
>>these days prohibit directly connecting power pins to either logic
>>supply. They require a resistor in the 1K to 10K range so that they
>>can drive it to the opposite level in automated test fixtures.
>That could find faults such as the output of an unused gate shorted to
>the supply rail, I suppose, but there must be few reasons for testing
>a logic state which never occurs in normal operation.
It allows for very dumb testing (which seems popular among test engineers).
If you can force every pin of a chip then you can call a standard library
function to test a chip of that type. Functionally testing a chip which is
usually brand new and just soldered into the PCB seems a bit pointless to
me but it does check that the right type of chip is in the hole i suppose.
Reply by Spehro Pefhany●July 12, 20042004-07-12
On Sun, 11 Jul 2004 15:03:52 -0500, the renowned Jack Klein
<jackklein@spamcop.net> wrote:
>On Sat, 10 Jul 2004 13:30:38 -0700, "Mike Turco"
><miketurco@yahoo-nospam4me.com> wrote in comp.arch.embedded:
>
>> If I want to tie CMOS (74HCXX) pins hi or low, do I need to use resistors?
>> If I need resistors, can I connect pins together and then tie them hi/lo
>> through a single resistor?
>
>You have had quite a few answers already, on both sides of the issue.
>With 74HC (but not 74HCT) it is not absolutely necessary as long as
>your power supply voltages will be fairly clean. And if they are too
>"unclean" you can have problems from the power supply pins anyway.
Clean? Unclean? You can tie CMOS logic inputs to power supply rails
with no problems. The logic transistion levels are related to the
supply rails in any case, and are always a fraction of them. The
supply rail is the very best CMOS logic level 0 or 1 that you can get
in a system without exceeding the supply rails.
With processor port pins, there is reason to use resistors if they can
become outputs that could try to pull the pin to the opposite state
(push-pull, or n-channel open-drain that is connected to the positive
supply rail etc.). This could happen with severe electrical disruption
(lightning strike, for example) and could possibly pull the supply
rail down in some systems and cause malfunctions that continue after
the disruption ends.
>On the other hand, the standards for many manufacturing organizations
>these days prohibit directly connecting power pins to either logic
>supply. They require a resistor in the 1K to 10K range so that they
>can drive it to the opposite level in automated test fixtures.
That could find faults such as the output of an unused gate shorted to
the supply rail, I suppose, but there must be few reasons for testing
a logic state which never occurs in normal operation.
Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
Reply by Jack Klein●July 11, 20042004-07-11
On Sat, 10 Jul 2004 13:30:38 -0700, "Mike Turco"
<miketurco@yahoo-nospam4me.com> wrote in comp.arch.embedded:
> If I want to tie CMOS (74HCXX) pins hi or low, do I need to use resistors?
> If I need resistors, can I connect pins together and then tie them hi/lo
> through a single resistor?
You have had quite a few answers already, on both sides of the issue.
With 74HC (but not 74HCT) it is not absolutely necessary as long as
your power supply voltages will be fairly clean. And if they are too
"unclean" you can have problems from the power supply pins anyway.
On the other hand, the standards for many manufacturing organizations
these days prohibit directly connecting power pins to either logic
supply. They require a resistor in the 1K to 10K range so that they
can drive it to the opposite level in automated test fixtures.
--
Jack Klein
Home: http://JK-Technology.Com
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>> Cmos is a high impeadance input that can be tied directly to either
>> sink or source without resistors, but the general design standard is
>> to use a single resistor to vcc as a "rail tie" for all high ties.
>
>Why?????
To make the board much, much harder to route. It's part of the
PWB Layout Union's rules and is required by the PWB designer
Full Employment Act of 1969 for all government contracts... :)
--
Guy Macon, Electronics Engineer & Project Manager for hire.
Remember Doc Brown from the _Back to the Future_ movies? Do you
have an "impossible" engineering project that only someone like
Doc Brown can solve? My resume is at http://www.guymacon.com/
><uguess@nowhere.net> wrote in message
>news:4on0f0hf8kmlb6ljoqof1nuai0iajop32m@4ax.com...
>> On Sat, 10 Jul 2004 13:30:38 -0700, "Mike Turco"
>> <miketurco@yahoo-nospam4me.com> wrote:
>>
>> >If I want to tie CMOS (74HCXX) pins hi or low, do I need to use
>resistors?
>> >If I need resistors, can I connect pins together and then tie them hi/lo
>> >through a single resistor?
>> >
>> Cmos is a high impeadance input that can be tied directly to either
>> sink or source without resistors, but the general design standard is
>> to use a single resistor to vcc as a "rail tie" for all high ties.
>
>Why?????
>
>I have seen many configuration pins on CPUs (also CMOS) directly tied to
>ground or VCC. Dip switches on microcontroller inputs (also CMOS) are often
>directly tied to ground. So what good does a resistor do?
>
>Meindert
>
You will have to ask those engineers who do so. Personally, with
CMOS, I tie directly.