Reply by -jg October 11, 20092009-10-11
On Oct 12, 2:41=A0am, "RIYA" <RIYAGIY...@GMAIL.COM> wrote:
> can anyone explain me to calculate the wait states needed? > Suppose we are using 120 nanosecond ROMs, which have valid data on the bu=
s
> 120 ns after the falling edge on the Output Enable line =A0with a clock r=
ate
> of 25 MHz (which means a clock cycle of 40 nanoseconds). =A0How many wait > states must the microprocessor insert into each bus cycle that reads from > the ROM? =A0
Homework ? - the Output enable time is not the only access time you need. Ask your tutor what the Address access time is, on these mythical '120ns ROMs' A wait state equation also do not tend to start from zero.(ie pass thru a virtual origin), so you need two numbers to calculate a wait state. -jg
Reply by Frank Buss October 11, 20092009-10-11
RIYA wrote:

> can anyone explain me to calculate the wait states needed? > Suppose we are using 120 nanosecond ROMs, which have valid data on the bus > 120 ns after the falling edge on the Output Enable line with a clock rate > of 25 MHz (which means a clock cycle of 40 nanoseconds). How many wait > states must the microprocessor insert into each bus cycle that reads from > the ROM?
Maybe 3 wait states? But you have to check the timing diagrams of the datasheets of the ROM and the microprocessor. "wait state" doesn't mean always the same and there could be other timing constants, e.g. how long the ROM needs to release the address bus after chip select release. Draw a timing diagrams on a big paper for your system and verify it with the datasheets. If you want to document it, this is a nice font for it: http://www.pcserviceselectronics.co.uk/fonts/ -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de
Reply by RIYA October 11, 20092009-10-11
can anyone explain me to calculate the wait states needed?
Suppose we are using 120 nanosecond ROMs, which have valid data on the bus
120 ns after the falling edge on the Output Enable line  with a clock rate
of 25 MHz (which means a clock cycle of 40 nanoseconds).  How many wait
states must the microprocessor insert into each bus cycle that reads from
the ROM?  

	   
					
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