"Jon Kirwan" <jonk@infinitefactors.org> wrote in message
news:3lurf55nvfa5j2q2r8a7sb10j3ne53sh28@4ax.com...
> On Fri, 13 Nov 2009 11:10:00 -0000, "Bill Davy" wrote:
>
>>"Bill Davy" <Bill@SynectixLtd.com> wrote in message
>>news:7m4mt3F3fs5haU1@mid.individual.net...
>>> "Joey.G" <jjoey.gold@gmail.com> wrote in message
>>> news:d4f2700e-0868-4b6d-ab04-f3480297d267@m38g2000yqd.googlegroups.com...
>>> On Nov 13, 5:16 am, Vladimir Vassilevsky <nos...@nowhere.com> wrote:
>>>> Bill Davy wrote:
>>>> > ADS1251 and 8051 Code
>>>> > Has anyone done this who can share the code? Just to save me time.
>>>>
>>>> Yes.
>>>>
>>>> > Any gotchas?
>>>>
>>>> Time is money.
>>>>
>>>> > I'd also quite like not to take every sample so I can use just the
>>>> > ADS1251
>>>> > to interrupt so it is both my clock and a data ready interrupt. I
>>>> > suppose
>>>> > it would be best to at least take one bit of the result.
>>>>
>>>> Anything you like.
>>>>
>>>> Vladimir Vassilevsky
>>>> DSP and Mixed Signal Design Consultanthttp://www.abvolt.com
>>>
>>> What Vladimir is trying to say is a project has 4 factors, quality,
>>> cost, time and experience.... changing only one of these factors
>>> effects the other factors
>>>
>>> Hence if you are in a hurry and have little experience and good
>>> quality is required.....expect to pay money for an answer or support
>>> from Vladimir.
>>>
>>> Joe
>>>
>>>
>>> ------------------------------
>>>
>>>
>>> In the past I have posted source code because when I started the
>>> Internet
>>> was a community not a marketplace. If Vladimir wishes to advertise his
>>> services or make snide remarks, perhaps he could find a different place
>>> (a
>>> kindergarten).
>>>
>>> I have been programming in assembler since 1972. I believe it is better
>>> to work as a team (but I am the only programmer on this project). I
>>> believe we see further if we stand on another's shoulders. I believe
>>> the
>>> Good Samaritan is still a good parable for society.
>>>
>>> Wanders off, shaking head sadly.
>>
>>Well, I have cobbled something together to get timing. Assuming Keil
>>compiler (though only using assembler). Two ADS1251 share an SCLK line
>>but
>>have separate Data Ready lines.
>
> Seems that they can't be daisy-chained, so that is the only easy way
> to go for two and minimum pin count to the micro.
>
>>Oh, and no cahrge for this.
>>
>>Bill
>
> I assume you have means by which you are elsewhere detecting the fact
> that the data is indeed ready (examining /DRDY, clearly.)
>
>> sbit SCLK = P0^0 ;
>> sbit DOR_A = P0^1 ;
>> sbit DOR_B = P0^2 ;
>> u8 ADC_A[4]; // little-endian
>>
>>void ReadADS1251(void)
>> {
>> #pragma asm
>>
>> ;
>> ; Build ADC_A in (R0,R1,R2) and ADC_B in (R3,R4,R5).
>> ; Use R6 to count 8 bits in.
>> ;
>> ;
>> ; This loop shifts eight bits in from each ADC, building the two values
>> in
>> ; the accumulator and the register which will hold the ADC_B byte.
>> ; There is no need to initialise either as all old bits are
>> ; shifted out.
>> ;
>> mov R6,#8 ; 2 cycles
>>Loop_0_3:
>> setb SCLK ; 2 cycles
>> mov c,DOR_A ; 2 cycles
>> rlc a ; 1 cycle
>> xch a,r3 ; 1 cycle
>> mov c,DOR_B ; 2 cycles
>> rlc a ; 1 cycle
>> xch a,r3 ; 1 cycle
>> clr SCLK ; 2 cycles
>> djnz r6,Loop_0_3 ; 3 cycles
>> ; Total = 15 cycles * 8 = 120
>> mov r0,a ; 1 cycle
>> ; Total for two bytes = 123 cycles
>><snip>
>
> That approach seems fine and fast. Your total is slightly wrong,
> though, isn't it? (The execution time for a pair of bytes from each
> converter is 15*7+14+2+1 which equals 122 cycles, not 123. You forgot
> that although the DJNZ is executed 8 times, one of those times it only
> requires 2 cycles, not 3, since the jump doesn't take place.)
>
> Some thoughts might be to also consider either an exact 50% duty cycle
> for SCLK or else to arrange it so that the initial value of SCLK
> before entering the loop doesn't matter (allowing you to 'play', if
> you want.)
>
> Shooting for 50% SCLK duty cycle requires an extra cycle per loop. In
> this case:
>
> .
> .
> .
> ; Assume DOR_A and DOR_B are valid upon entry.
> ; SCLK assumed LOW to start and is operated at
> ; a very clean 50% duty cycle (8 cycles low
> ; and 8 cycles high.)
> mov r7, #8 ; reserved for bottom byte loop
> mov r6, #8 ; used for top and middle byte loops
> top_loop:
> mov c, DOR_A
> rlc a
> setb SCLK
> xch a, r3
> mov c, DOR_B
> rlc a
> xch a, r3
> mov r0, a
> clr SCLK
> djnz r6, top_loop
> mov r6, #8
> mid_loop:
> mov c, DOR_A
> setb SCLK
> rlc a
> xch a, r4
> mov c, DOR_B
> rlc a
> xch a, r4
> clr SCLK
> mov r1, a
> djnz r6, mid_loop
> bot_loop:
> mov c, DOR_A
> rlc a
> setb SCLK
> xch a, r5
> mov c, DOR_B
> rlc a
> xch a, r5
> mov r2, a
> clr SCLK
> djnz r7, bot_loop
> .
> .
> .
>
> Whether or not you actually care about a clean 50% duty cycle is
> another matter, of course.
>
> If not, perhaps changing things so that the initial value of SCLK
> before entering the loop doesn't matter:
>
> ; Assume DOR_A and DOR_B are valid upon entry.
> ; Initial value of SCLK doesn't matter and the
> ; duty cycle is close to 33%/66%.
> mov r6, #8
> top_loop:
> mov c, DOR_A
> rlc a
> mov c, DOR_B
> cpl SCLK
> xch a, r3
> rlc a
> xch a, r3
> cpl SCLK
> djnz r6, top_loop
> mov r0, a
> .
> .
> .
>
> Not much different, really. And your initial code was just fine. Just
> some minor twists on what you've already done.
>
> Jon
Thanks for that input Jon and I am grateful to hear you say I am on the
right track. There is no pressure on a 50% duty cycle, so we will see how
it works. I must admit I seldom worry about the DJNZ being 2 once as in
reality things are not going to work if that matters (it allows me an error
in the other direction elsewhere).
There are some shenanigans about holding DOUT for some fairly precise number
of cycles to force devices sharing SCLK to fall into synchronisation.
That's going to be another stage of the battle.
I was hoping TI (or someone) would have done this for n*ADS1251 sharing an
SCLK. Hopefully, when I have done it (if, works, etc) I will post a copy
here for the record.
Regards,
Bill