Thanks for this link. I have tried the test given there to check for
missing memory chip.
But in my case, the controller hangs if I try to access the memory
which is not connected. When I am using JTAG to debug this, it shows
"emulation running" message.
Any inputs on this?
Reply by RCIngham●May 18, 20102010-05-18
>On May 15, 9:52=A0pm, larwe <zwsdot...@gmail.com> wrote:
>> On May 15, 1:15=A0pm, Bhavik <bhavik.pa...@gmail.com> wrote:
>>
>> > still work if I setup a bigger value of rows and columns, but It
would
>> > create memory aliasing problem (or feature!), which I want to avoid.
>>
>> SO CONFIGURE FOR THE WIDEST POSSIBILITY AND TEST FOR THE MEMORY
>> ALIASING. Sheesh, this is what I and others have been telling you.
>
>Thanks all for the help. I am now able to correct memory width and
>size configuration.
>I still have one problem. The approach suggested here works only if
>there is a memory connected on given chip select.
>
>Is it possible to find if the memory is actually present on a given
>chip select?
>I have a device which has 256MB SDRAM on cs0, but there is no memory
>on cs1. I tried reading some status registers for cs1, but they look
>the same as cs0.
>So I can't determine if the memory is actually present there.
>
On May 15, 9:52=A0pm, larwe <zwsdot...@gmail.com> wrote:
> On May 15, 1:15=A0pm, Bhavik <bhavik.pa...@gmail.com> wrote:
>
> > still work if I setup a bigger value of rows and columns, but It would
> > create memory aliasing problem (or feature!), which I want to avoid.
>
> SO CONFIGURE FOR THE WIDEST POSSIBILITY AND TEST FOR THE MEMORY
> ALIASING. Sheesh, this is what I and others have been telling you.
Thanks all for the help. I am now able to correct memory width and
size configuration.
I still have one problem. The approach suggested here works only if
there is a memory connected on given chip select.
Is it possible to find if the memory is actually present on a given
chip select?
I have a device which has 256MB SDRAM on cs0, but there is no memory
on cs1. I tried reading some status registers for cs1, but they look
the same as cs0.
So I can't determine if the memory is actually present there.
Reply by larwe●May 15, 20102010-05-15
On May 15, 1:15=A0pm, Bhavik <bhavik.pa...@gmail.com> wrote:
> still work if I setup a bigger value of rows and columns, but It would
> create memory aliasing problem (or feature!), which I want to avoid.
SO CONFIGURE FOR THE WIDEST POSSIBILITY AND TEST FOR THE MEMORY
ALIASING. Sheesh, this is what I and others have been telling you.
Reply by Bhavik●May 15, 20102010-05-15
On May 13, 11:40=A0pm, rickman <gnu...@gmail.com> wrote:
> On May 13, 11:39=A0am, Rob Gaddi <rga...@technologyhighland.com> wrote:
>
>
>
> > On 5/12/2010 8:42 AM, Bhavik wrote:
>
> > > Hello,
>
> > > I am working on an embedded device in which I need to configure LPDDR
> > > memory.
> > > Since LPDDR does not always support SRR (status register read)
> > > function, I need to find the data width of the memory manually, and
> > > configure the system memory controller accordingly.
>
> > > Can someone suggest a way to find this?
>
> > > Thanks for help in advance.
>
> > Wait, what kind of embedded device don't you already know what the data
> > width of the memory is? =A0Don't you have a line item on a BOM somewher=
e
> > that tells you everything you need to know about the RAM?
>
> Maybe the guy writing the software doesn't know who is buying the
> hardware next year?
>
> Rick
Lot of replies!!
The reason why I want to know about data width of the memory is
because I need to setup number of Rows and Columns in the memory
controller.
And these settings depend on the data width of the memory. It can
still work if I setup a bigger value of rows and columns, but It would
create memory aliasing problem (or feature!), which I want to avoid.
And I want to write a generic code which can be used for different
memory sizes and data widths, since my code is going to run on the
same platform with different memory configurations. I already have
devices with different memory configuration on different chip selects,
and there might be more such devices. FYI, I am writing code for
Qualcomm qsd8250 platform.
Reply by rickman●May 13, 20102010-05-13
On May 13, 11:39=A0am, Rob Gaddi <rga...@technologyhighland.com> wrote:
> On 5/12/2010 8:42 AM, Bhavik wrote:
>
> > Hello,
>
> > I am working on an embedded device in which I need to configure LPDDR
> > memory.
> > Since LPDDR does not always support SRR (status register read)
> > function, I need to find the data width of the memory manually, and
> > configure the system memory controller accordingly.
>
> > Can someone suggest a way to find this?
>
> > Thanks for help in advance.
>
> Wait, what kind of embedded device don't you already know what the data
> width of the memory is? =A0Don't you have a line item on a BOM somewhere
> that tells you everything you need to know about the RAM?
Maybe the guy writing the software doesn't know who is buying the
hardware next year?
Rick
Reply by D Yuniskis●May 13, 20102010-05-13
Hi Rob,
Rob Gaddi wrote:
> Wait, what kind of embedded device don't you already know what the data
> width of the memory is? Don't you have a line item on a BOM somewhere
> that tells you everything you need to know about the RAM?
<grin> I often design flexible memory configurations in
products and probe for "what's available" during bootstrap.
I had one design that supported single *bit* increments
in memory widths! :>
Reply by D Yuniskis●May 13, 20102010-05-13
Marc Jet wrote:
> Please elaborate about the problem.
>
> You say that "the memory controller seems to perform 2 writes of 16
> bits". However you also say that you're the one to "configure the
> system memory controller".
>
> Can't you just configure it for 32 bit access, and then do the
-----------------^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
That's the key. *EXPLICITLY* set it to 32b wide. Probe
the memory (taking care to understand how a "floating bus"
will be read!!) and determine if it is, in fact, 32b wide.
If not, configure for 16b.
I suspect the OP's problem is the controller defaults to
16b mode. So, the 32b write gets broken into two contiguous
16b writes. Regardless of the actual RAM installed, both
of these writes will succeed -- and read back properly.
BECAUSE THERE IS ALWAYS AT LEAST 16b WIDE MEMORY PRESENT!
The OP needs to *deliberately* force the controller to
operate in 32b mode *before* making his first probe...
> suggested 0xaaaabbbb test in 32 bit mode, and then configure the
> controller AGAIN according to the test result?
>
> Or, if it comes (magically) preconfigured, can't you just read the
> configuration registers and thus know what type of memory is currently
> configured?
Reply by Rob Gaddi●May 13, 20102010-05-13
On 5/12/2010 8:42 AM, Bhavik wrote:
> Hello,
>
> I am working on an embedded device in which I need to configure LPDDR
> memory.
> Since LPDDR does not always support SRR (status register read)
> function, I need to find the data width of the memory manually, and
> configure the system memory controller accordingly.
>
> Can someone suggest a way to find this?
>
> Thanks for help in advance.
Wait, what kind of embedded device don't you already know what the data
width of the memory is? Don't you have a line item on a BOM somewhere
that tells you everything you need to know about the RAM?
--
Rob Gaddi, Highland Technology
Email address is currently out of order
Reply by larwe●May 13, 20102010-05-13
On May 13, 6:46=A0am, Marc Jet <jetm...@hotmail.com> wrote:
> You say that "the memory controller seems to perform 2 writes of 16
> bits". =A0However you also say that you're the one to "configure the
I kind of gave up after reading the OP's second response. If the
memory controller is splitting one 32-bit access into two 16-bit
accesses, then either it's configured for 16 bit mode or it's broken.