Hey, thanks for the tips ! > RGB to YIQ is just a matrix multiply (with offsets). Actually I changed my mind, I decided to cheat for my first attempt. Instead of going RGB I'm borrowing the 16 old C64 colors and just using a lookip table instead. The tricky part seems to be modulating the color subcarrier. Do I have to use a sine lookup table and a multiply, or can I get away with just modulating a square wave ? eg square wave on -> output color signal, square wave off -> output nothing ? Or will the quality be really cruddy ? > > Remember that your pixel clock is ~9Mhz for 480x480 and ~12Mhz for > 640x480. > Um, is that NTSC or PAL ? I'm using a 320x200 screen with an 8.18MHz dot clock. Can you actually get useable output of 640x480 with a 12MHz clock ? (This is going to be an rf modulated signal) Wouldn't that be too wide for the screen ? Also, does the dot clock have to be phase coherent with the color subcarrier ? I noticed it was on the C64 and was wondering if this was needed for good quality ? Also, does the phase of the color burst have to be in phase with the burst of the previous scanline ? It'd be easier to control if it wasn't. Does the scanline period have to be an even multiple of the color subcarrier frequency ? > You'll probably want a PLL for that. If you can, oversample your outputs > as it'll look a lot better. I'm using the ICS525-01 frequency synthesizer on the BurchEd Spartan board to generate a 16x burst (57.27272MHz - which is divided by two for cpu/system clock) The 57MHz is used to index a 16 entry sine lookup table to do the color subcarrier modulation. I'm clocking the output using the 57MHz clock (of course the DAC will only work to about 12MHz... :) . Does that count as oversampling ? will the frequency synthesizer be accurate enough ? And do I have to go to this extreme to produce a modulated signal ? > > Also remember that if you're going to a TV, you're going to have to > interlace your output. That means a half-line at the bottom of the even > field and a half-line at the top of the odd field. :) > I thought I did't have to do that as long as the equalization pulses were fudged appropriately. Is this necessary ? IE will it wreck the TV ? Or is the quality of the output really bad ? Sorry for bombarding you and the newsgroup with a whole lot of questions, it just seems like you know what you're talking about, and I thought there might be other people interested. I think I can implement and entire C64 system in the FPGA minus a few components like memory and the DAC. IT might make a good student project, eg implement your favorite computer system of the 70's in the FPGA. (I hope Commodore doesn't mind, but it is a clean room implementation.) When I get this all figured out, I'll post a simplified version on my website. PS. I found out the answer to an earlier question about how fast external ram could be cycled. When the clock of the SoC was bumped up to 29MHz would fail at random intervals. So I inserted a wait state for the ram and voila! everything works okay again. Hmmm, might be better to use a lower clock frequency. Rob

> The next mini-project I'm attempting is color TV output from the > FPGA. It should be possible to do an RGB to YIQ conversion and > produce a digital modulated color signal which can then be fed to an > external DAC (DAC-08) for output to a TV. RGB to YIQ is just a matrix multiply (with offsets). Remember that your pixel clock is ~9Mhz for 480x480 and ~12Mhz for 640x480. You'll probably want a PLL for that. If you can, oversample your outputs as it'll look a lot better. Also remember that if you're going to a TV, you're going to have to interlace your output. That means a half-line at the bottom of the even field and a half-line at the top of the odd field. :) Keith -- Keith D. Shapiro http://www.torilive.org/

I've managed to get Lee Davison's EnhBASIC working on my 6502 SoC. (The hard part was getting the 6502 core to work properly.) Lee's EnhBASIC was a snap to make use of. I've reduced the size of the core down to about 650 LUTs, so it should easily fit in a 10k device (although I haven't tried it). I think it's possible to reduce the core size down below 600 LUTs by using a reduced address bus width and substituting tri-state buffers for logic multiplexer's. I've posted the source on my website at http://www.birdcomputer.ca/bc6502_page.html The next mini-project I'm attempting is color TV output from the FPGA. It should be possible to do an RGB to YIQ conversion and produce a digital modulated color signal which can then be fed to an external DAC (DAC-08) for output to a TV. Rob