Have a look in the index of the technology manual. I am off on holiday now!
Cheers.
Robert.
-----Original Message-----
From: Manfield Chow [mailto:]
Sent: Wednesday, July 31, 2002 9:33 AM
To:
Subject: Re: [fpga-cpu] Re: 16 X 16 multiplier
Hi Robert,
In your reply, you said: >You can also get the tool to create a pipelined
multiplier by providing a series of registers >after the multiplier. I am not very understand how to create a pipelined multiplier by
LeonardoSpectrum.
Would you mind to tell me more details?
Thanks
Reala
----- Original Message -----
From: "Jeffery, Robert" <>
To: <>
Sent: Monday, July 29, 2002 9:30 PM
Subject: RE: [fpga-cpu] Re: 16 X 16 multiplier
> Hi Folks.
>
> If you are using a synthesis tool such as LeonardoSpectrum from Mentor
> Graphics all you need do is use the code:
>
> a*b
>
> the tool will build an efficient multiplier for you. You can also get
the
> tool to create a pipelined multiplier by providing a series of registers
> after the multiplier. The results are good giving about a 2X improvement
> over non pipelined. Here are some results:
>
> Altera FLEX 10K P & R Area (LCs) Delay, ns Mhz
> non-pipelined 541 27.4 36.49
> pipelined 587 12.8 78.12
> Xilinx Virtex P & R Area (LCs) Delay, ns Mhz
> non-pipelined 156 23.353 42.82
> pipelined 192 11.268 88.75
>
> An alternative approach would be to use the CoreGen multipliers and use
> instantiation.
>
> If you are using virtexII parts these have dedicated 18X18 multipliers
> builtin. The synthesis tool will automatically use these rather than
> building a multiplier using LUT's since they aremore efficient and
faster.
>
> If you are using Xilinx or Altera you can get their OEM versions of
> LeonardoSpectrum to try out or goto the Mentor Graphics webpage for a
eval
> copy to download goto http://www.mentor.com/leonardospectrum/
>
> Hope this helps.
>
> Cheers.
>
> Robert.
> -----Original Message-----
> From: Manfield Chow [mailto:]
> Sent: Saturday, July 27, 2002 1:49 AM
> To:
> Subject: Re: [fpga-cpu] Re: 16 X 16 multiplier
> Rob,
>
> I try to search in internet to find 16 X 16 multiplier, but it seems
that
> the
> information is not detailed enough.
> So, I hope to "find" a multiplier by synthesis tools.
>
> Reala
> ----- Original Message -----
> From: "rtfinch36" <>
> To: <>
> Sent: Saturday, July 27, 2002 12:15 AM
> Subject: [fpga-cpu] Re: 16 X 16 multiplier
> > Just another thought. Does it have to be a generic 16x16 multiplier
?
> > Or can you get away with a constant coefficient type multiplier ?
> >
> > Rob
> >
> >
> >
> > To post a message, send it to:
> > To unsubscribe, send a blank message to:
>
> >
> > ">http://docs.yahoo.com/info/terms/ > >
>
> To post a message, send it to:
> To unsubscribe, send a blank message to:
> ">http://docs.yahoo.com/info/terms/
> To post a message, send it to:
> To unsubscribe, send a blank message to:
In your reply, you said: >You can also get the tool to create a pipelined
multiplier by providing a series of registers >after the multiplier. I am not very understand how to create a pipelined multiplier by
LeonardoSpectrum.
Would you mind to tell me more details?
Thanks
Reala
----- Original Message -----
From: "Jeffery, Robert" <>
To: <>
Sent: Monday, July 29, 2002 9:30 PM
Subject: RE: [fpga-cpu] Re: 16 X 16 multiplier
> Hi Folks.
>
> If you are using a synthesis tool such as LeonardoSpectrum from Mentor
> Graphics all you need do is use the code:
>
> a*b
>
> the tool will build an efficient multiplier for you. You can also get
the
> tool to create a pipelined multiplier by providing a series of registers
> after the multiplier. The results are good giving about a 2X improvement
> over non pipelined. Here are some results:
>
> Altera FLEX 10K P & R Area (LCs) Delay, ns Mhz
> non-pipelined 541 27.4 36.49
> pipelined 587 12.8 78.12
> Xilinx Virtex P & R Area (LCs) Delay, ns Mhz
> non-pipelined 156 23.353 42.82
> pipelined 192 11.268 88.75
>
> An alternative approach would be to use the CoreGen multipliers and use
> instantiation.
>
> If you are using virtexII parts these have dedicated 18X18 multipliers
> builtin. The synthesis tool will automatically use these rather than
> building a multiplier using LUT's since they aremore efficient and
faster.
>
> If you are using Xilinx or Altera you can get their OEM versions of
> LeonardoSpectrum to try out or goto the Mentor Graphics webpage for a
eval
> copy to download goto http://www.mentor.com/leonardospectrum/
>
> Hope this helps.
>
> Cheers.
>
> Robert.
> -----Original Message-----
> From: Manfield Chow [mailto:]
> Sent: Saturday, July 27, 2002 1:49 AM
> To:
> Subject: Re: [fpga-cpu] Re: 16 X 16 multiplier
> Rob,
>
> I try to search in internet to find 16 X 16 multiplier, but it seems
that
> the
> information is not detailed enough.
> So, I hope to "find" a multiplier by synthesis tools.
>
> Reala
> ----- Original Message -----
> From: "rtfinch36" <>
> To: <>
> Sent: Saturday, July 27, 2002 12:15 AM
> Subject: [fpga-cpu] Re: 16 X 16 multiplier
> > Just another thought. Does it have to be a generic 16x16 multiplier
?
> > Or can you get away with a constant coefficient type multiplier ?
> >
> > Rob
> >
> >
> >
> > To post a message, send it to:
> > To unsubscribe, send a blank message to:
>
> >
> > ">http://docs.yahoo.com/info/terms/ > >
>
> To post a message, send it to:
> To unsubscribe, send a blank message to:
> ">http://docs.yahoo.com/info/terms/
> To post a message, send it to:
> To unsubscribe, send a blank message to:
Lattice recently bought Lucent's ORCA FPGA product
line and their prices are usually lower.
--- "Jeffery, Robert" <>
wrote: > Hi Reala.
>
> I am assuming you want to build the design in an
> FPGA. If this is correct
> then you'll probably look at Xilinx, Altera or Actel
> although there are
> several other possible candidates. If you use Xilinx
> then they have a set of
> paramatised building blocks. These include blocks
> like arithmetic operators;
> _, +, x, /, sqroot or memories etc. The tool for
> generating these blocks is
> called CoreGen. You can learn more about this tool
> and the whole Xilinx
> toolset by visiting their website at www.xilinx.com.
> The same is true for
> Altera and Actel and again I would encourage you to
> take a look at their
> websites, www.altera.com and www.actel.com.
>
> A pipelined multiplier will generate a new output
> every clock cycle but will
> have a latency, that is a delay of several clock
> cycles before the outputs
> start to come out. So whether you can suffer a
> latency will depend on your
> design requirements. You can always build a single
> clock cycle multiplier
> but the inherent delay will grow dramatically as the
> input size grows. That
> is the trade off.
>
> As I mention above you will find lots of great
> information about these
> topics on these websites so do go and take a look.
>
> Hope that helps.
>
> Cheers.
>
> Robert.
>
> -----Original Message-----
> From: Manfield Chow
> [mailto:]
> Sent: Tuesday, July 30, 2002 2:30 AM
> To:
> Subject: Re: [fpga-cpu] Re: 16 X 16 multiplier
> Hi Robert,
>
> Thank you for your email.
> I get LeonardoSpectrum now. I try to familar this.
> What is "CoreGen multipliers and use instantiation"?
> Should I need another software to do this? Thanks.
> Moreover, I need to design a 1 cycle per instruction
> (eg. multiply) core.
> Can pipelined multiplier achieve this requirement?
> It seems that it take
> more than 1 cycle.
> As I am a beginner , I confuse the relationship
> between pipeline and
> operation cycle.
>
> Thank you.
> Reala
>
> ----- Original Message -----
> From: "Jeffery, Robert" <>
> To: <>
> Sent: Monday, July 29, 2002 9:30 PM
> Subject: RE: [fpga-cpu] Re: 16 X 16 multiplier
> > Hi Folks.
> >
> > If you are using a synthesis tool such as
> LeonardoSpectrum from Mentor
> > Graphics all you need do is use the code:
> >
> > a*b
> >
> > the tool will build an efficient multiplier for
> you. You can also get the
> > tool to create a pipelined multiplier by providing
> a series of registers
> > after the multiplier. The results are good giving
> about a 2X improvement
> > over non pipelined. Here are some results:
> >
> > Altera FLEX 10K P & R Area (LCs) Delay, ns Mhz
> > non-pipelined 541 27.4 36.49
> > pipelined 587 12.8 78.12
> > Xilinx Virtex P & R Area (LCs) Delay, ns Mhz
> > non-pipelined 156 23.353 42.82
> > pipelined 192 11.268 88.75
> >
> > An alternative approach would be to use the
> CoreGen multipliers and use
> > instantiation.
> >
> > If you are using virtexII parts these have
> dedicated 18X18 multipliers
> > builtin. The synthesis tool will automatically use
> these rather than
> > building a multiplier using LUT's since they
> aremore efficient and faster.
> >
> > If you are using Xilinx or Altera you can get
> their OEM versions of
> > LeonardoSpectrum to try out or goto the Mentor
> Graphics webpage for a eval
> > copy to download goto
> http://www.mentor.com/leonardospectrum/
> >
> > Hope this helps.
> >
> > Cheers.
> >
> > Robert.
> >
> >
> > -----Original Message-----
> > From: Manfield Chow
> [mailto:]
> > Sent: Saturday, July 27, 2002 1:49 AM
> > To:
> > Subject: Re: [fpga-cpu] Re: 16 X 16 multiplier
> >
> >
> > Rob,
> >
> > I try to search in internet to find 16 X 16
> multiplier, but it seems that
> > the
> > information is not detailed enough.
> > So, I hope to "find" a multiplier by synthesis
> tools.
> >
> > Reala
> > ----- Original Message -----
> > From: "rtfinch36" <>
> > To: <>
> > Sent: Saturday, July 27, 2002 12:15 AM
> > Subject: [fpga-cpu] Re: 16 X 16 multiplier
> >
> >
> > > Just another thought. Does it have to be a
> generic 16x16 multiplier ?
> > > Or can you get away with a constant coefficient
> type multiplier ?
> > >
> > > Rob
> > >
> > >
> > >
> > > To post a message, send it to:
>
> > > To unsubscribe, send a blank message to:
> >
> > >
> > > ">http://docs.yahoo.com/info/terms/
> > >
> > >
> >
> >
> > To post a message, send it to:
>
> > To unsubscribe, send a blank message to:
> >
> >
> > ">http://docs.yahoo.com/info/terms/
> >
> >
> > To post a message, send it to:
>
> > To unsubscribe, send a blank message to:
>
> >
> > ">http://docs.yahoo.com/info/terms/
> >
> >
>
> To post a message, send it to:
>
> To unsubscribe, send a blank message to:
>
>
> ">http://docs.yahoo.com/info/terms/
> To post a message, send it to:
=== message truncated ===
__________________________________________________
Reply by Jeffery, Robert●July 30, 20022002-07-30
Hi Reala.
I am assuming you want to build the design in an FPGA. If this is correct
then you'll probably look at Xilinx, Altera or Actel although there are
several other possible candidates. If you use Xilinx then they have a set of
paramatised building blocks. These include blocks like arithmetic operators;
_, +, x, /, sqroot or memories etc. The tool for generating these blocks is
called CoreGen. You can learn more about this tool and the whole Xilinx
toolset by visiting their website at www.xilinx.com. The same is true for
Altera and Actel and again I would encourage you to take a look at their
websites, www.altera.com and www.actel.com.
A pipelined multiplier will generate a new output every clock cycle but will
have a latency, that is a delay of several clock cycles before the outputs
start to come out. So whether you can suffer a latency will depend on your
design requirements. You can always build a single clock cycle multiplier
but the inherent delay will grow dramatically as the input size grows. That
is the trade off.
As I mention above you will find lots of great information about these
topics on these websites so do go and take a look.
Hope that helps.
Cheers.
Robert.
-----Original Message-----
From: Manfield Chow [mailto:]
Sent: Tuesday, July 30, 2002 2:30 AM
To:
Subject: Re: [fpga-cpu] Re: 16 X 16 multiplier
Hi Robert,
Thank you for your email.
I get LeonardoSpectrum now. I try to familar this.
What is "CoreGen multipliers and use instantiation"?
Should I need another software to do this? Thanks.
Moreover, I need to design a 1 cycle per instruction (eg. multiply) core.
Can pipelined multiplier achieve this requirement? It seems that it take
more than 1 cycle.
As I am a beginner , I confuse the relationship between pipeline and
operation cycle.
Thank you.
Reala
----- Original Message -----
From: "Jeffery, Robert" <>
To: <>
Sent: Monday, July 29, 2002 9:30 PM
Subject: RE: [fpga-cpu] Re: 16 X 16 multiplier
> Hi Folks.
>
> If you are using a synthesis tool such as LeonardoSpectrum from Mentor
> Graphics all you need do is use the code:
>
> a*b
>
> the tool will build an efficient multiplier for you. You can also get
the
> tool to create a pipelined multiplier by providing a series of registers
> after the multiplier. The results are good giving about a 2X improvement
> over non pipelined. Here are some results:
>
> Altera FLEX 10K P & R Area (LCs) Delay, ns Mhz
> non-pipelined 541 27.4 36.49
> pipelined 587 12.8 78.12
> Xilinx Virtex P & R Area (LCs) Delay, ns Mhz
> non-pipelined 156 23.353 42.82
> pipelined 192 11.268 88.75
>
> An alternative approach would be to use the CoreGen multipliers and use
> instantiation.
>
> If you are using virtexII parts these have dedicated 18X18 multipliers
> builtin. The synthesis tool will automatically use these rather than
> building a multiplier using LUT's since they aremore efficient and
faster.
>
> If you are using Xilinx or Altera you can get their OEM versions of
> LeonardoSpectrum to try out or goto the Mentor Graphics webpage for a
eval
> copy to download goto http://www.mentor.com/leonardospectrum/
>
> Hope this helps.
>
> Cheers.
>
> Robert.
> -----Original Message-----
> From: Manfield Chow [mailto:]
> Sent: Saturday, July 27, 2002 1:49 AM
> To:
> Subject: Re: [fpga-cpu] Re: 16 X 16 multiplier
> Rob,
>
> I try to search in internet to find 16 X 16 multiplier, but it seems
that
> the
> information is not detailed enough.
> So, I hope to "find" a multiplier by synthesis tools.
>
> Reala
> ----- Original Message -----
> From: "rtfinch36" <>
> To: <>
> Sent: Saturday, July 27, 2002 12:15 AM
> Subject: [fpga-cpu] Re: 16 X 16 multiplier
> > Just another thought. Does it have to be a generic 16x16 multiplier
?
> > Or can you get away with a constant coefficient type multiplier ?
> >
> > Rob
> >
> >
> >
> > To post a message, send it to:
> > To unsubscribe, send a blank message to:
>
> >
> > ">http://docs.yahoo.com/info/terms/ > >
>
> To post a message, send it to:
> To unsubscribe, send a blank message to:
> ">http://docs.yahoo.com/info/terms/
> To post a message, send it to:
> To unsubscribe, send a blank message to:
Thank you for your email.
I get LeonardoSpectrum now. I try to familar this.
What is "CoreGen multipliers and use instantiation"?
Should I need another software to do this? Thanks.
Moreover, I need to design a 1 cycle per instruction (eg. multiply) core.
Can pipelined multiplier achieve this requirement? It seems that it take
more than 1 cycle.
As I am a beginner , I confuse the relationship between pipeline and
operation cycle.
Thank you.
Reala
----- Original Message -----
From: "Jeffery, Robert" <>
To: <>
Sent: Monday, July 29, 2002 9:30 PM
Subject: RE: [fpga-cpu] Re: 16 X 16 multiplier
> Hi Folks.
>
> If you are using a synthesis tool such as LeonardoSpectrum from Mentor
> Graphics all you need do is use the code:
>
> a*b
>
> the tool will build an efficient multiplier for you. You can also get
the
> tool to create a pipelined multiplier by providing a series of registers
> after the multiplier. The results are good giving about a 2X improvement
> over non pipelined. Here are some results:
>
> Altera FLEX 10K P & R Area (LCs) Delay, ns Mhz
> non-pipelined 541 27.4 36.49
> pipelined 587 12.8 78.12
> Xilinx Virtex P & R Area (LCs) Delay, ns Mhz
> non-pipelined 156 23.353 42.82
> pipelined 192 11.268 88.75
>
> An alternative approach would be to use the CoreGen multipliers and use
> instantiation.
>
> If you are using virtexII parts these have dedicated 18X18 multipliers
> builtin. The synthesis tool will automatically use these rather than
> building a multiplier using LUT's since they aremore efficient and
faster.
>
> If you are using Xilinx or Altera you can get their OEM versions of
> LeonardoSpectrum to try out or goto the Mentor Graphics webpage for a
eval
> copy to download goto http://www.mentor.com/leonardospectrum/
>
> Hope this helps.
>
> Cheers.
>
> Robert.
> -----Original Message-----
> From: Manfield Chow [mailto:]
> Sent: Saturday, July 27, 2002 1:49 AM
> To:
> Subject: Re: [fpga-cpu] Re: 16 X 16 multiplier
> Rob,
>
> I try to search in internet to find 16 X 16 multiplier, but it seems
that
> the
> information is not detailed enough.
> So, I hope to "find" a multiplier by synthesis tools.
>
> Reala
> ----- Original Message -----
> From: "rtfinch36" <>
> To: <>
> Sent: Saturday, July 27, 2002 12:15 AM
> Subject: [fpga-cpu] Re: 16 X 16 multiplier
> > Just another thought. Does it have to be a generic 16x16 multiplier
?
> > Or can you get away with a constant coefficient type multiplier ?
> >
> > Rob
> >
> >
> >
> > To post a message, send it to:
> > To unsubscribe, send a blank message to:
>
> >
> > ">http://docs.yahoo.com/info/terms/ > >
>
> To post a message, send it to:
> To unsubscribe, send a blank message to:
> ">http://docs.yahoo.com/info/terms/
> To post a message, send it to:
> To unsubscribe, send a blank message to:
If you are using a synthesis tool such as LeonardoSpectrum from Mentor
Graphics all you need do is use the code:
a*b
the tool will build an efficient multiplier for you. You can also get the
tool to create a pipelined multiplier by providing a series of registers
after the multiplier. The results are good giving about a 2X improvement
over non pipelined. Here are some results:
Altera FLEX 10K P & R Area (LCs) Delay, ns Mhz
non-pipelined 541 27.4 36.49
pipelined 587 12.8 78.12
Xilinx Virtex P & R Area (LCs) Delay, ns Mhz
non-pipelined 156 23.353 42.82
pipelined 192 11.268 88.75
An alternative approach would be to use the CoreGen multipliers and use
instantiation.
If you are using virtexII parts these have dedicated 18X18 multipliers
builtin. The synthesis tool will automatically use these rather than
building a multiplier using LUT's since they aremore efficient and
faster.
If you are using Xilinx or Altera you can get their OEM versions of
LeonardoSpectrum to try out or goto the Mentor Graphics webpage for a eval
copy to download goto http://www.mentor.com/leonardospectrum/
Hope this helps.
Cheers.
Robert.
-----Original Message-----
From: Manfield Chow [mailto:]
Sent: Saturday, July 27, 2002 1:49 AM
To:
Subject: Re: [fpga-cpu] Re: 16 X 16 multiplier
Rob,
I try to search in internet to find 16 X 16 multiplier, but it seems that
the
information is not detailed enough.
So, I hope to "find" a multiplier by synthesis tools.
Reala
----- Original Message -----
From: "rtfinch36" <>
To: <>
Sent: Saturday, July 27, 2002 12:15 AM
Subject: [fpga-cpu] Re: 16 X 16 multiplier
> Just another thought. Does it have to be a generic
16x16 multiplier ?
> Or can you get away with a constant coefficient type multiplier ?
>
> Rob
>
> To post a message, send it to:
> To unsubscribe, send a blank message to:
I try to search in internet to find 16 X 16 multiplier, but it seems that
the
information is not detailed enough.
So, I hope to "find" a multiplier by synthesis tools.
Reala
----- Original Message -----
From: "rtfinch36" <>
To: <>
Sent: Saturday, July 27, 2002 12:15 AM
Subject: [fpga-cpu] Re: 16 X 16 multiplier
> Just another thought. Does it have to be a generic
16x16 multiplier ?
> Or can you get away with a constant coefficient type multiplier ?
>
> Rob
>
> To post a message, send it to:
> To unsubscribe, send a blank message to:
If it is possible, Would mind to tell me the name of the IEEE paper about
multiplexer?
I also want study this paper.
Thanks a lot.
Reala
----- Original Message -----
From: "Bala Subramani.C" <>
To: <>
Sent: Thursday, July 25, 2002 3:14 PM
Subject: Re: [fpga-cpu] 16 X 16 multiplier
> HI reala,
> Once i had an oppurtunity to go thro a design of a
> multiplier which was using a DSP algorithm(multiplexer
> based array multiplier some ieee paper done by one of
> my collegue. I worked on synthesising and it worked at
> some 8.5ns delay(combinational) (can fit into 90Mhz
> -single clock) and it took around 125-130 LUTs in
> virtexII.Sorry i duuno any details abt embedded
> multiplier in xilinx but try to contact any xilxinx
> represntative for that info.
> chk out one of such represntative Mr.Sanket at this id
>
> Bets of luck.
> Bala.C
>
> --- Manfield Chow <>
> wrote:
> > Hi Bala,
> >
> > Thank you for your help.
> >
> > For more details, we would like to design a
> > multiplier for DSP chip.
> > One feature of DSP chip is one cycle for
> > multiplication. If i design the
> > multiplier directly, I afraid that the size of
> > multiplier will be too big.
> > So, I want to know how to design a multiplier for
> > DSP chip.
> >
> > Yes, I know that dedicated multiplier in virtexII.
> > Then, If i want to translate the design from FPGA to
> > ASIC.
> > How to translate the dedicated multiplier to our
> > ASIC?
> > Can I get the design of this multiplier?
> > Or pay the money to buy the design of this
> > multiplier from Xilinx?
> >
> > Thanks
> > Reala
> >
> > ----- Original Message -----
> > From: "Bala Subramani.C" <>
> > To: <>
> > Sent: Thursday, July 25, 2002 12:12 PM
> > Subject: Re: [fpga-cpu] 16 X 16 multiplier
> >
> >
> > > HI Reala,
> > > Implementing a multiplier in a single clk
> > means
> > > that u gotta use some combinational logic whose
> > delay
> > > is 1/frequncy.It will take some logic(any good
> > digital
> > > book gives an idea abt multipliers(i ahve read one
> > in
> > > smith book (ASIC))also u ahve lot of info in the
> > net
> > > regarding combl multipliers.If u go for sequential
> > > ones it will take less logic and give good freq
> > also
> > > with reduced logic when compared to combl ones.U
> > can
> > > even try pipelining a combl multipliuer urself.
> > > P.S:U also have a dedicated multiplier in virtexII
> > > which will be implemented by leospec if u jus use
> > * in
> > > ur design chk it out too.its faster and fine.
> > > Best of luck :)
> > > Rgds,
> > > Bala.C
> > >
> > > --- Manfield Chow <>
> > > wrote:
> > > > Hadi, Sridhar,
> > > >
> > > > Thank you for your reply.
> > > > the clock frequency is not too high. It should
> > be
> > > > 20Mhz to 40Mhz.
> > > > My boss tells me that if we implement 16X16
> > > > multiplier directly,
> > > > the size will be very big. So, I want to know
> > some
> > > > technic to design a
> > > > single cycle 16X16 multiplier to reduce this
> > size.
> > > > Moreover, If i implement the design by FPGA,
> > then
> > > > change to ASIC.
> > > > As there are specific blocks in FPGA (eg. Logic
> > > > block , lookup table), how
> > > > can i put this in my ASIC? some tools to do
> > this? or
> > > > buy library from FPGA's
> > > > vender?
> > > > or some format of files (eg. netlist) generate
> > by
> > > > FPGA tools which can be
> > > > read by ASIC layout design tools?
> > > >
> > > > Thank you for your help.
> > > >
> > > > With best regards,
> > > > Reala
> > >
> > >
> > > __________________________________________________
> > >
> > > To post a message, send it to:
> >
> > > To unsubscribe, send a blank message to:
> >
> > >
> > > ">http://docs.yahoo.com/info/terms/
> > >
> > >
> >
> >
> > To post a message, send it to:
> >
> > To unsubscribe, send a blank message to:
> >
> >
> > ">http://docs.yahoo.com/info/terms/
> >
>
> __________________________________________________
>
> To post a message, send it to:
> To unsubscribe, send a blank message to:
HI reala,
Once i had an oppurtunity to go thro a design of a
multiplier which was using a DSP algorithm(multiplexer
based array multiplier some ieee paper done by one of
my collegue. I worked on synthesising and it worked at
some 8.5ns delay(combinational) (can fit into 90Mhz
-single clock) and it took around 125-130 LUTs in
virtexII.Sorry i duuno any details abt embedded
multiplier in xilinx but try to contact any xilxinx
represntative for that info.
chk out one of such represntative Mr.Sanket at this id
Bets of luck.
Bala.C
--- Manfield Chow <>
wrote: > Hi Bala,
>
> Thank you for your help.
>
> For more details, we would like to design a
> multiplier for DSP chip.
> One feature of DSP chip is one cycle for
> multiplication. If i design the
> multiplier directly, I afraid that the size of
> multiplier will be too big.
> So, I want to know how to design a multiplier for
> DSP chip.
>
> Yes, I know that dedicated multiplier in virtexII.
> Then, If i want to translate the design from FPGA to
> ASIC.
> How to translate the dedicated multiplier to our
> ASIC?
> Can I get the design of this multiplier?
> Or pay the money to buy the design of this
> multiplier from Xilinx?
>
> Thanks
> Reala
>
> ----- Original Message -----
> From: "Bala Subramani.C" <>
> To: <>
> Sent: Thursday, July 25, 2002 12:12 PM
> Subject: Re: [fpga-cpu] 16 X 16 multiplier
> > HI Reala,
> > Implementing a multiplier in a single clk
> means
> > that u gotta use some combinational logic whose
> delay
> > is 1/frequncy.It will take some logic(any good
> digital
> > book gives an idea abt multipliers(i ahve read one
> in
> > smith book (ASIC))also u ahve lot of info in the
> net
> > regarding combl multipliers.If u go for sequential
> > ones it will take less logic and give good freq
> also
> > with reduced logic when compared to combl ones.U
> can
> > even try pipelining a combl multipliuer urself.
> > P.S:U also have a dedicated multiplier in virtexII
> > which will be implemented by leospec if u jus use
> * in
> > ur design chk it out too.its faster and fine.
> > Best of luck :)
> > Rgds,
> > Bala.C
> >
> > --- Manfield Chow <>
> > wrote:
> > > Hadi, Sridhar,
> > >
> > > Thank you for your reply.
> > > the clock frequency is not too high. It should
> be
> > > 20Mhz to 40Mhz.
> > > My boss tells me that if we implement 16X16
> > > multiplier directly,
> > > the size will be very big. So, I want to know
> some
> > > technic to design a
> > > single cycle 16X16 multiplier to reduce this
> size.
> > > Moreover, If i implement the design by FPGA,
> then
> > > change to ASIC.
> > > As there are specific blocks in FPGA (eg. Logic
> > > block , lookup table), how
> > > can i put this in my ASIC? some tools to do
> this? or
> > > buy library from FPGA's
> > > vender?
> > > or some format of files (eg. netlist) generate
> by
> > > FPGA tools which can be
> > > read by ASIC layout design tools?
> > >
> > > Thank you for your help.
> > >
> > > With best regards,
> > > Reala
> >
> >
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Reala
----- Original Message -----
From: "Eric Smith" <>
To: <>
Sent: Thursday, July 25, 2002 2:58 PM
Subject: Re: [fpga-cpu] 16 X 16 multiplier
> > Actually, my boss request single cycle.
>
> OK, but a pipelined multiplier is still considered single cycle, in
> that every cycle you can start a new multiply.
>
> > Moreover, MAC - multiply-adder module is another difficult task for
me.
> > If multiple is not single cycle, MAC will be very slow. Am I
correct?
>
> Pipelined multiply works just fine for MAC.
>
> Let's say you're going to do a series of 50 MACs, and you have a
pipelined
> multiplier with a three-cycle latency. Your operands are A0..A49 and
> B0..B49. Further, let's assume that your accumulator takes one cycle.
> multiplier multiplier accumulator
> inputs output output
> (multiplicands) (product) (sum of products)
> --------------- ---------- -----------------
> Cycle 0: input A0, B0 don't care don't care
> Cycle 1: input A1, B1 don't care don't care
> Cycle 2: input A2, B2 don't care don't care
> Cycle 3: input A3, B3 A0*B0 force zero
> Cycle 4: input A4, B4 A1*B1 A0*B0
> Cycle 5: input A5, B5 A2*B2 A0*B0+A1*B1
> Cycle 6: input A6, B6 A3*B3 Sum for i = 0 to 2 of Ai*Bi
> Cycle 7: input A7, B7 A4*B4 Sum for i = 0 to 3 of Ai*Bi
> ....
> Cycle 49: input A49, B49 A46*B46 Sum for i = 0 to 45 of Ai*Bi
> Cycle 50: don't care A47*B47 Sum for i = 0 to 46 of Ai*Bi
> Cycle 51: don't care A48*B48 Sum for i = 0 to 47 of Ai*Bi
> Cycle 52: don't care A49*B49 Sum for i = 0 to 48 of Ai*Bi
> Cycle 53: don't care don't care Sum for i = 0 to 49 of Ai*Bi
> As you can see, you've completed 50 MACs in 54 cycles, even though
the
> total time to compute one MAC is 4 cycles.
>
> As I said before, a pipelined parallel multiplier will generally take
> as much space as a flow-through parallel multiplier. But a pipelined
> parallel multiplier with a latency of three can typically be cycled
> almost three times faster than the flow-through multiplier, so you get
> nearly three times the total data throughput.
>
>
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